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AR8327-AL1A-R Datasheet(PDF) 372 Page - List of Unclassifed Manufacturers |
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AR8327-AL1A-R Datasheet(HTML) 372 Page - List of Unclassifed Manufacturers |
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372 / 394 page ![]() 372 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch Atheros Communications, Inc. 372 • June 2011 COMPANY CONFIDENTIAL 3.10.29 Debug Register — RGMII Mode Selection Address Offset: 0x012, or 0d18 Table 3-394 summarizes the Register Table 3-394. Debug Register — RGMII Mode Selection 3 DBG_LINK_OK_10 0T Mode R/W For link management use. The forced LINK_OK_100BT HW Rst 0 SW Rst 0 2 DBG_LINK_OK_10 00T Mode R/W For link management use. The forced LINK_OK_1000BT HW Rst 0 SW Rst 0 1 DBG_LINK_RDY_1 00T Mode R/W For link management use. The forced LINK_RDY_100BT HW Rst 0 SW Rst 0 0 DBG_EN_EN Mode R/W For link management use. When this bit is set, the test bits in this register take effect. HW Rst 0 SW Rst 0 Table 3-393. Hib Control and Auto Negotiation Test Register Bit Symbol Type Description Bit Symbol Type Description 15:14 RES Mode R/W Reserved HW Rst 01 SW Rst Retain 13:12 RES Mode R/W Reserved HW Rst 00 SW Rst Retain 11 RES Mode R/W Reserved HW Rst 1 SW Rst Retain 10 RES Mode R/W Reserved HW Rst 1 SW Rst Retain 9:6 RES Mode RO Reserved HW Rst 0 SW Rst 0 |
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