Everest Semiconductor

Confidential

ES7243

Revision 10.0

4

March 2019

Latest datasheet: www.everest-semi.com or info@everest-semi.com

3. CLOCK MODES AND SAMPLING FREQUENCIES

The device supports standard audio clocks (256Fs, 384Fs, 512Fs, etc), USB clocks (12/24 MHz),

and some common non standard audio clocks (25 MHz, 26 MHz, etc).

According to the serial audio data sampling frequency (Fs), the device can work in two speed

modes: single speed mode or double speed mode. In single speed mode, Fs normally ranges

from 8 kHz to 48 kHz, and in double speed mode, Fs normally range from 64 kHz to 96 kHz.

The device can work either in master clock mode or slave clock mode. In slave mode, LRCK and

SCLK are supplied externally, and LRCK and SCLK must be synchronously derived from the

system clock with specific rates. In master mode, LRCK and SCLK are derived internally from

device master clock.

4. MICRO-CONTROLLER CONFIGURATION INTERFACE

controller can completely configure the device through writing to internal configuration

registers.

line (CCLK) for data transfer. The timing diagram for data transfer of this interface is given in

Figure 1a and Figure 1b. Data are transmitted synchronously to CCLK clock on the CDATA line on

a byte-by-byte basis. Each bit in a byte is sampled during CCLK high with MSB bit being

transmitted firstly. Each transferred byte is followed by an acknowledge bit from receiver to pull

the CDATA low. The transfer rate of this interface can be up to 400 kbps.

A master controller initiates the transmission by sending a “start” signal, which is defined as a

high-to-low transition at CDATA while CCLK is high. The first byte transferred is the slave address.

It is a seven-bit chip address followed by a RW bit. The chip address must be 0010 0x, where x

equals ̴AD1 ̴AD0. The RW bit indicates the slave data transfer direction. Once an acknowledge

bit is received, the data transfer starts to proceed on a byte-by-byte basis in the direction

specified by the RW bit. The master can terminate the communication by generating a “stop”

signal, which is defined as a low-to-high transition at CDATA while CCLK is high.

instructions are shown in Table 1 and Table 2. Please note that, to read data from a register, you

must set R/W bit to 0 to access the register address and then set R/W to 1 to read data from the

register.

Chip Address

R/W

Register Address

Data to be written

start

0010 0 ̴AD1 ̴AD0

0

ACK

RAM

ACK

DATA

ACK

Stop