GD25Q80CEFG datasheet(32/67 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q80C

Figure 26. Read Identification ID Sequence Diagram

7.24.

High Performance Mode (HPM) (A3H)

The High Performance Mode (HPM) command must be executed prior to Dual or Quad I/O commands when

operating at high frequencies (see fR and fC1 in AC Electrical Characteristics). This command allows pre-charging of

internal charge pumps so the voltages required for accessing the flash memory array are readily available. The

command sequence: CS# goes lowSending A3H command Sending 3-dummy ByteCS# goes high. See Figure

27. After the HPM command is executed, HPF bit of status register will be set to 1, the device will maintain a slightly

higher standby current (Icc9) than standard SPI operation. The Release from Power-Down or HPM command (ABH) can

be used to return to standard SPI standby current (Icc1). In addition, Power-Down command (B9H) will also release

the device from HPM mode back to standard SPI standby state.

Figure 27. High Performance Mode Sequence Diagram

CS#

SCLK

9 10

MSB

18 19 20 21

22 23

26 27 28 29

30 31

Capacity

JDID7-JDID0

CS#

SCLK

MSB

Memory Type

JDID15-JDID8

11 12 13 14 15

9FH

Manufacturer ID

MSB

Command

2 3

A3H

CS#

SCLK

29 30 31

MSB

3 Dummy Bytes

23 22

High Performance Mode

HPM

GD25Q80CEFG Datasheet(PDF) 32 Page - GigaDevice Semiconductor (Beijing) Inc.

GD25Q80CEFG Datasheet(HTML) 32 Page - GigaDevice Semiconductor (Beijing) Inc.

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