© VITESSE SEMICONDUCTOR CORPORATION

Page 13

9/6/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8140

2.48832Gb/s 16:1 SONET/SDH

Transceiver with Integrated Clock Generator

G52251-0, Rev. 4.0

Supplies

The VSC8140 is specified as a PECL device with a single positive 3.3V supply. Should the user desire to

Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is

also be placed in parallel with the 0.1

µF and 0.01µF capacitors mentioned above. Recommended capacitors are

low-inductance ceramic SMT X7R devices. For the 0.1

µF capacitor, a 0603 package should be used. The

0.01

µF and 0.001µF capacitors can be either 0603 or 0403 packages.

maintain the optimal jitter and loop bandwidth characteristics of the PLL contained in the VSC8140, the analog

power supply pins should be filtered from the main power supply with a 10

µH C-L-C pi filter. If preferred, a

ferrite bead may be used to provide the isolation. The 0.1

µF and 0.01µF decoupling capacitors are still required

and must be connected to the supply pins between the device and the C-L-C pi filter (or ferrite bead).

For low frequency decoupling, 47

µF tantalum low-inductance SMT caps are sprinkled over the board’s

main +3.3V power supply and placed close to the C-L-C pi filter.

If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling

Figure 17: PLL Power Supply Decoupling Scheme

Note: V

10

µH

0.1

µF

0.1

µF

0.01

µF