DM9801
1M Home Phoneline Network Physical Layer Single Chip Transceiver
6
Preliminary
Version: DM9801-DS-P02
March 20, 2000
Pin Description (Continued)
PHY Address Interface:
PHYAD[4:0] provides up to 32 unique PHY address. An address selection of all zeros (00000) will result in a
PHY isolation condition. See the isolate bit description in the BMCR, address 00.
68
PHYADSEL
(PHYAD0)
Or
SCLK
I/O,Z
MII Serial Management PHY Address Select (MII Mode, INTFSEL = 0):
PHYADSEL is an input signal that selects one of two PHY addresses within
the 32 address range for the DM9801 MII management interface when both
CONFIG1 and CONFIG0 are not set to 1.
0 = 0x01 address
1 = 0x1F address
PHY Address 0 (MII Mode, INTFSEL = 0):
PHY address bit 0 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1.
Serial Interface Clock (GPSI Mode, INTFSEL = 1):
SCLK is a bi-directional clock signal used to synchronize SI, SO and SCS#
to and from the DM9801 SPI bus.
8
PHYAD1
I/O,
Z
PHY Address 1 (MII Mode, INTFSEL = 0):
PHY address bit 1 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
9
PHYAD2
I/O,
Z
PHY Address 2 (MII Mode, INTFSEL = 0):
PHY address bit 2 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
10
PHYAD3
I/O,
Z
PHY Address 3 (MII Mode, INTFSEL = 0):
PHY address bit 3 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
47
PHYAD4
I/O,
Z
PHY Address 4 (MII Mode, INTFSEL = 0):
PHY address bit 4 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
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