3

AT84AS003

5403AS–BDC–10/04

Functional

Description

The AT84AS003 is a 10-bit 1.5 Gsps ADC combined with a high-speed demultiplexer

(DMUX) used to lower the LVDS output bit stream (10-bit data and one out-of range bit)

by a factor of 2 or 4.

The ADC works in fully differential mode from the analog input to the digital outputs. It

provides an on-chip 100

Ω differential termination for the clock input. The analog input is

500 mVpp on a 100

Ω differential input impedance. 50Ω reverse terminations are

required for the analog input. They should be placed as close as possible to the EBGA

package input pins (2 mm maximum). The output clock and the output data are LVDS

compatible (100

Ω differentially terminated).

The AT84AS003 ADC features two asynchronous resets:

•

DRRB, which ensures that the first digitized data corresponds to the first acquisition

•

ASYNCRST, which initializes the DMUX

The gain control pin GA is used to finely adjust the ADC gain to a unity gain.

The control pin B/GB is provided to select either a binary or gray data output format.

A Sampling Delay Adjust function (SDA, activated via the SDAEN signal) may be used

to fine-tune the ADC aperture delay by approximately 120 ps around its nominal value.

This function is useful when interleaving multiple ADCs.

The control pin B/GB is provided to select either a binary or Gray data output format.

A tunable delay cell (controlled via CLKDACTRL) is integrated between the ADC and

the DMUX on the clock path to fine-tune the data according to the clock alignment at the

interface between the ADC and the DMUX. This delay can be tuned from -250 to 250 ps

around a default center value, featuring a 500 ps typical tuning range. No tuning should

be necessary for operating frequencies up to 1.5 Gsps.

An extra stand-alone delay cell is also provided. It is controlled via analog DACTRL con-

trol input and activated via DAEN. The tuning range is typically 500 ps.

A pattern generator (PGEB) is integrated in the ADC block for debugging purposes or

acquisition setup. Similarly, a Built-in Self Test (BIST) is provided for quick debug of the

DMUX block.

The demultiplexer ratio can be selected using RS (1:2 or 1:4 ratio).

Two modes for the output clock (via DRTYPE) are selectable:

•

DR mode: only the output clock’s rising egde is active, the output clock rate is the

same as the output data rate

•

DR/2 mode: both the output clock’s rising and falling edges are active, the output

clock rate is half the output data rate

The AT84AS003’s data is output in two different modes:

•

Staggered: even and odd bits are output with half a data period delay

•

Simultaneous: even and odd bits are output at the same time

A sleep mode is provided to lower the power consumption of the DMUX block.

Die junction temperature monitoring is also provided to facilitate management of the

junction temperature, by sensing the voltage drop across two diodes implemented on

the ADC and DMUX respectively, close to the chip’s hot point.

The AT84AS003 is delivered in an Enhanced Ball Grid Array (EBGA). Its TCE, which is

similar to that of the FR4 material, makes it highly suitable for applications exposed to

large thermal variations.