MSM80C86A-10JS datasheet(13/37 Pages) OKI

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¡ Semiconductor

MSM80C86A-10RS/GS/JS

Maximum Mode (continued)

VIH

VIL

AD15 - AD0

See NOTE 3, 4

CLK (MSM82C84A-2 Output)

S2, S1, S0 (Except Halt)

MSM82C88-2 Outputs

See NOTES 5, 6

MSM82C88-2 Outputs

See NOTES 5, 6

INTA Cycle

tCHSV

DEN

AMWC or AIOWC

MWTC or IOWC

MCE/

PDEN

DT/R

INTA

DEN

Write Cycle

AD15 - AD0

S2, S1, S0

Software Halt

(DEN = VOL; RD, MRDC, IORC, MWTC,

AMWC, IOWC, AIOWC, INTA = VOH)

tCLAV

tCLSH

tCLAX

tCLDV

tCVNX

tCLML

tCLMH

tCLML

tCLMH

tDVCL

tCLDX

tCHDTH

tCLMH

tCVNX

tCVNV

tCLAV

tCLML

tCHDTL

tCLMCH

tSVMCH

tCVNX

tCLAZ

tCVNV

Data

(See

NOTE 8)

Pointer

Float

Invalid Address

tCHDX

Float

Notes: 1. All signals switch between VOH and VOL unless otherwise specified.

2. RDY is sampled near the end of T2, T3, TW to determine if TW machines

states are to be inserted.

3. Cascade address is valid between first and second INTA cycle.

4. Two INTA cycles run back-to-back. The MSM80C86A-10 LOCAL ADDR/

DATA BUS is floating during both INTA cycles. Control for pointer address

is shown for second INTA cycle.

5. Signals at MSM82C84A-2 or MSM82C88-2 are shown for reference only.

6. The issuance of the MSM 82C88-2 command and control signals (MRDC,

MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active

high MSM82C88-2 CEN.

7. All timing measurements are made at 1.5 V unless otherwise noted.

8. Status inactive in state just prior to T4

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