PCM1791A datasheet(17/58 Pages) TI

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PCM1791A

SLES071A − MARCH 2003 − REVISED JANUARY 2004

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AUDIO DATA INTERFACE

Audio Serial Interface

The audio interface port is a 3-wire serial port. It includes LRCK (pin 1), BCK (pin 2), and DATA (pin 3). BCK is the

serial audio bit clock, and it is used to clock the serial data present on DATA into the serial shift register of the audio

interface. Serial data is clocked into the PCM1791A on the rising edge of BCK. LRCK is the serial audio left/right word

clock.

The PCM1791A requires the synchronization of LRCK and the system clock, but does not need a specific phase

relationship between LRCK and the system clock.

If the relationship between LRCK and system clock changes more than

±6 BCK, internal operation is initialized within

1/fS and analog outputs are forced to the bipolar zero level until resynchronization between LRCK and the system

clock is completed.

PCM Audio Data Formats and Timing

The PCM1791A supports industry-standard audio data formats, including standard right-justified, I2S, and

left-justified. The data formats are shown in Figure 28. Data formats are selected using the format bits, FMT[2:0],

in control register 18. The default data format is 24-bit I2S. All formats require binary 2s complement, MSB-first audio

data. Figure 27 shows a detailed timing diagram for the serial audio interface.

DATA

t(BCH)

1.4 V

BCK

LRCK

t(BCL)

t(LB)

t(BCY)

t(DS)

t(DH)

1.4 V

t(BL)

PARAMETERS

MIN

MAX

UNITS

t(BCY)

BCK pulse cycle time

t(BCL)

BCK pulse duration, LOW

t(BCH)

BCK pulse duration, HIGH

t(BL)

BCK rising edge to LRCK edge

t(LB)

LRCK edge to BCK rising edge

t(DS)

DATA setup time

t(DH)

DATA hold time

—

LRCK clock data

50%

± 2 bit clocks

Figure 27. Timing of Audio Interface

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