6

MPC7455 Part Number Specification for the XPC74x5RXnnnNx Series

MOTOROLA

General Parameters

General Parameters

Table 13 provides the L3 bus AC timing specifications for PB2 and Late Write SRAMs for the MPC7455

part numbers described herein.

Table 13. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs

At recommended operating conditions. See Table 4.

Parameter

Symbol

All Speed Grades

Unit

Notes

Min

Max

Min

Max

L3_CLK rise and fall

time

—

1.0

—

1.0

ns

1, 5

Setup times:

Data and parity

1.5

—

1.5

—

ns

2, 5

Input hold times:

Data and parity

—

0.5

—

0.5

ns

2, 5

Valid times:

Data and parity

—

ns

3, 4, 5

Valid times:

All other outputs

—

ns

4

Output hold times:

Data and parity

—

—

ns

3, 4, 5

Output hold times:

All other outputs

—

—

ns

4, 5

L3_CLK to high

impedance:

Data and parity

—2.0

—2.0

ns

5

L3_CLK to high

impedance:

All other outputs

—2.0

—2.0

ns

5

Notes:

2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising

edge of the input L3_ECHO_CLKn (see Figure 10 in the MPC7455 RISC Microprocessor Hardware Specifications).

Input timings are measured at the pins.

3. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLKn to the midpoint of

the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive

50-

Ω load (see Figure 10 in the MPC7455 RISC Microprocessor Hardware Specifications).

launched by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid

and output hold times such that the specified output signal will be valid for approximately one L3_CLK period

starting three-fourths of a clock prior to the edge on which the SRAM will sample it and ending one-fourth of a clock

period after the edge it will be sampled.

5. Timing behavior and characterization are currently being evaluated.

6. These configuration bits allow the AC timing of the L3 interface to be altered via software. They must be both set or

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