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¡ Semiconductor

MSM82C54-2RS/GS/JS

Reading Counter Values

All MSM82C54-2 counting is down-counting, the counting being in steps of 2 in mode 3.

Counter values can be read during counting by. (1) direct reading, (2) counter latching (“read

on the fly”), and (3) read back command.

(1) Direct reading

Counter values can be read by direct reading operations.

Since the counter value read according to the timing of the RD and CLK signals is not

guaranteed, it is necessary to stop the counting by a gate input signal, or to interrupt the

clock input temporarily by an external circuit to ensure that the counter value is correctly

read.

(2) Counter latching

In this method, the counter value is latched by writing counter latch command, thereby

enabling a stable value to be read without effecting the counting in any way at all. The

output latch (OL) of the selected counter latches the count value when a counter latch

command is written. The count value is held until it is read by the CPU or the control word

is set again.

If a counter latch command is written again before reading while a certain counter is latched,

the second counter latch command is ignored and the value latched by the first counter latch

command is maintained.

The MSM82C54-2 features independent reading and writing from and to the same counter.

When a counter is programmed for the 2-byte counter value, the following sequence is

possible:

1. Count value (LSB) reading

2. New count value (LSB) writing

3. Count value (MSB) reading

4. New count value (MSB) writing

An example of a counter latching program is given below.

Counter latching executed for counter #1 (Read/Load 2-byte setting)

0 1 0 0 ¥ ¥ ¥ ¥

MVI A

Denotes counter latching

OUT n3

Write in control word address (n3)

IN n1

Reading of the LSB of the counter value

latched from counter #1.

n1: Conter #1 address

MOV B, A

IN n1

MOV C, A

Reading of MSB from counter #1

The counter value at this point is latching