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HPZB01P-IPEX Datasheet(PDF) 4 Page - HOPE Microelectronics CO., Ltd. |
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HPZB01P-IPEX Datasheet(HTML) 4 Page - HOPE Microelectronics CO., Ltd. |
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4 / 14 page ![]() HPZB01 /HPZB01P V1.0 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com Pin# Signal HPZB01 Signal HPZB01P Direction Description PA5 PA5 I/O Digital I/O ADC5 ADC5 Analog ADC input 5 PTI_DATA PTI_DATA O Data signal of packet trace interface(PTI) nBOOTMODE nBOOTMODE I Embedded serial bootloader activation out of reset 19 TRACEDATA3 TRACEDATA3 O Synchronous CPU trace data bit 3 PA6 PA6 I/O High current Digital I/O TIM1C3 TIM1C3 O Timer 1 channel 3 output 20 TIM1C3 TIM1C3 I Timer 1 channel 3 input PB1 PB1 I/O Digital I/O SC1MISO SC1MISO O SPI slave data out of serial controller 1 SC1MOSI SC1MOSI O SPI master data out of serial controller 1 SC1SDA SC1SDA I/O TWI data of serial controller 1 SC1TXD SC1TXD O UART transmit data of serial controller 1 TIM2C1 TIM2C1 O Timer 2 channel 1 output 21 TIM2C1 TIM2C1 I Timer 2 channel 1 input PB2 PB2 I/O Digital I/O SC1MISO SC1MISO I SPI master data in of serial controller 1 SC1MOSI SC1MOSI I SPI slave data in of serial controller 1 SC1SC SC1SC I/O TWI clock of serial controller 1 SC1RXD SC1RXD I UART receive data of serial controller 1 TIM2C2 TIM2C2 O Timer 2 channel 2 output 22 TIM2C2 TIM2C2 I Timer 2 channel 2 input JTCK JTCK I JTAG clock input from debugger 23 SWCLK SWCLK I/O Serial Wire Clock input/output with debugger PC2 PC2 I/O Digital I/O JTDO JTDO O JTAG data out to debugger 24 SWO SWO O Serial Wire Output asynchronous trace output to debugger PC3 PC3 I/O Digital I/O 25 JTDI JTDI I JTAG data in from debugger PC4 PC4 I/O Digital I/O JTMS JTMS I JTAG mode select from debugger 26 SWDIO SWDIO I/O Serial Wire bidirectional data to/from debugger PC1 PC1 I/O Digital I/O ADC3 ADC3 Analog ADC input 3 SWO SWO O Serial Wire Output asynchronous trace output to debugger 27 TRACEDATA0 TRACEDATA0 O Synchronous CPU trace data bit 0 PC0 PC0 I/O High current Digital I/O JRST JRST I JTAG reset input from debugger IRQD1 IRQD1 I Default external interrupt source D 28 TRACEDATA1 TRACEDATA1 O Synchronous CPU trace data bit 1 |
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