NM14F2KSLAXCL-3BNA datasheet(59/121 Pages) NANYA

59 / 121 page

Version 1.6

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 2Gb LPDDR2

NM148(F)2KSLAXCL/NM1482NSLAXCL

NTC Proprietary

Level: Property

(17)Reliability Guidance

This reliability guidance is intended to notify some guidance related to using NAND flash with 8bit ECC for each

512 bytes. For detailed reliability data, please refer to TOSHIBA’s reliability note.

Although random bit errors may occur during use, it does not necessarily mean that a block is bad.

Generally, a block should be marked as bad when a program status failure or erase status failure is detected.

The other failure modes may be recovered by a block erase.

ECC treatment for read data is mandatory due to the following Data Retention and Read Disturb failures.

 Write/Erase Endurance

Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a status read

after either an auto program or auto block erase operation. The cumulative bad block count will increase

along with the number of write/erase cycles.

 Data Retention

The data in memory may change after a certain amount of storage time. This is due to charge loss or charge

gain. After block erasure and reprogramming, the block may become usable again.

Here is the combined characteristics image of Write/Erase Endurance and Data Retention.

 Read Disturb

A read operation may disturb the data in memory. The data may change due to charge gain. Usually, bit

errors occur on other pages in the block, not the page being read. After a large number of read cycles

(between block erases), a tiny charge may build up and can cause a cell to be soft programmed to another

state. After block erasure and reprogramming, the block may become usable again.

NM14F2KSLAXCL-3BNA Datasheet(PDF) 59 Page - Nanya Technology Corporation.