M48T86PC1F datasheet(12/29 Pages) ARTSCHIP

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M48T86

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Table 3. Time, Calendar, and Alarm Formats

Interrupts

The RTC plus RAM includes three separate, fully

automatic sources of interrupt (alarm, periodic, up-

date-in-progress) available to a processor. The

alarm interrupt can be programmed to occur at

rates from once per second to once per day. The

periodic interrupt can be selected from rates of

500ms to 122µs. The update-ended interrupt can

be used to indicate that an update cycle has com-

pleted.

The processor program can select which inter-

rupts, if any, are going to be used. Three bits in

to an interrupt-enable bit (Register B; Bit 6 = PIE;

Bit 5 = AIE; Bit 4 = UIE) permits an interrupt to be

initialized when the event occurs. A '0' in an inter-

rupt-enable bit prohibits the IRQ pin from being as-

serted from that interrupt condition. If an interrupt

flag is already set when an interrupt is enabled,

IRQ is immediately set at an active level, although

the interrupt initiating the event may have occurred

much earlier. As a result, there are cases where

the program should clear such earlier initiated in-

terrupts before first enabling new interrupts.

When an interrupt event occurs, the related flag bit

(Register C; Bit 6 = PF; Bit 5 = AF; Bit 4 = UF) is

set to a logic '1.' These flag bits are set indepen-

dent of the state of the corresponding enable bit in

out enabling the corresponding enable bits. The

interrupt flag bits are status bits which software

can interrogate as necessary.

When a flag is set, an indication is given to soft-

ware that an interrupt event has occurred since the

flag bit was last read; however, care should be tak-

en when using the flag bits as all are cleared each

time Register C is read. Double latching is includ-

ed with Register C so that bits which are set re-

main stable throughout the READ cycle. All bits

which are set high are cleared when read. Any

new interrupts which are pending during the READ

cycle are held until after the cycle is completed.

One, two, or three bits can be set when reading

ined when read to ensure that no interrupts are

lost.

The second flag bit usage method is with fully en-

abled interrupts. When an interrupt flag bit is set

and the corresponding enable bit is also set, the

IRQ pin is asserted low. IRQ is asserted as long as

at least one of the three interrupt sources has its

flag and enable bits both set. The IRQF Bit (Reg-

ister C; Bit 7) is a '1' whenever the IRQ pin is being

driven low. Determination that the RTC initiated an

interrupt is accomplished by reading Register C. A

logic '1' in the IRQF Bit indicates that one or more

interrupts have been initiated by the M48T86. The

act of reading Register C clears all active flag bits

and the IRQF Bit.

Address

RTC Bytes

Range

Decimal

Binary

BCD

Seconds

0-59

00-3B

00-59

Seconds Alarm

0-59

00-3B

00-59

Minutes

0-59

00-3B

00-59

Minutes Alarm

0-59

00-3B

00-59

Hours, 12-hrs

1-12

01-0C AM

81-8C PM

01-12 AM

81-92 PM

Hours, 24-hrs

0-23

00-17

00-23

Hours Alarm, 12-hrs

1-12

01-0C AM

81-8C PM

01-12 AM

81-92 PM

Hours Alarm, 24-hrs

0-23

00-17

00-23

Day of Week (1 = Sun)

1-7

01-07

Day of Month

1-31

01-1F

01-31

Month

1-12

01-0C

01-12

Year

0-99

00-63

00-99

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