SC4524FEVB datasheet(15/23 Pages) SEMTECH

15 / 23 page

SC4524F

Applications Information (Cont.)

Loop Compensation

The goal of compensation is to shape the frequency

response of the converter so as to achieve high DC

accuracy and fast transient response while maintaining

loop stability.

The block diagram in Figure 7 shows the control loops of a

buck converter with the SC4524F. The inner loop (current

loop) consists of a current sensing resistor (R

s=5.5mW) and

a current amplifier (CA) with gain (G

CA=18.5). The outer

loop (voltage loop) consists of an error amplifier (EA), a

PWM modulator, and a LC filter.

Since the current loop is internally closed, the remaining

task for the loop compensation is to design the voltage

compensator (C

5, R7, and C8).

Figure 7 — Block diagram of control loops

For a converter with switching frequency F

SW, output

inductance L

1, output capacitance CO and loading R, the

control (V

C) to output (VO) transfer function in Figure 7 is

given by:

This transfer function has a finite DC gain

an ESR zero F

Z at

Fig.7

Resr

CO M P

REF

CO NTRO LLER AND SCHOTTKY DIO DE

PW M

M O DULATO R

Vram p

Fig.7

Resr

CO M P

REF

CO NTRO LLER AND SCHOTTKY DIO DE

PW M

M O DULATO R

Vram p

a dominant low-frequency pole F

P at

and double poles at half the switching frequency.

Including the voltage divider (R

4 and R6), the control to

feedback transfer function is found and plotted in Figure

8 as the converter gain.

Since the converter gain has only one dominant pole at

low frequency, a simple Type-2 compensation network

is sufficient for voltage loop compensation. As shown in

Figure 8, the voltage compensator has a low frequency

integrator pole, a zero at F

Z1, and a high frequency pole

at F

P1. The integrator is used to boost the gain at low

frequency. The zero is introduced to compensate the

excessive phase lag at the loop gain crossover due to the

integrator pole (-90deg) and the dominant pole (-90deg).

The high frequency pole nulls the ESR zero and attenuates

high frequency noise.

Figure 8 — Bode plots for voltage loop design

Therefore, the procedure of the voltage loop design for

the SC4524F can be summarized as:

(1) Plot the converter gain, i.e. control to feedback transfer

function.

(2) Select the open loop crossover frequency, F

C, between

Fig.8

Fsw/2

Fz1

Fp1

10K

100K

10M

-60

-30

FREQUENCY (Hz)

CONVE

RTER

GAIN

LOOP

GAIN

COMP

ENSAT

OR GA

Fig.8

Fsw/2

Fz1

Fp1

10K

100K

10M

-60

-30

FREQUENCY (Hz)

CONVE

RTER

GAIN

LOOP

GAIN

COMP

ENSAT

OR GA

)

/ω

s/ω

)

s/ω

)

ESR

PWM

≈

ESR

ω =

ω ≈

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