A4964 datasheet(24/92 Pages) ALLEGRO

24 / 92 page

Sensorless Sinusoidal Drive BLDC Controller

A4964

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

If ESF = 1 and the A4964 internal junction temperature, TJ, rises

above the overtemperature threshold, TJF, the regulator is imme-

diately shut down and MRSTn will go low. All A4964 functions

other than the regulator remain active. When TJ drops by more

than the overtemperature hysteresis below the overtemperature

threshold (TJ < TJF – TJHyst), the regulator will remain shut

down and MRSTn will remain low for 10 ms. After this timeout,

MRSTn goes high and the regulator is re-enabled and attempts

to restart. If an undervoltage shutdown and an overtemperature

warning occur simultaneously, both must be cleared to allow the

regulator to restart.

Internal A4964 logic circuitry is not powered from the VLR regu-

lator and remains fully operational regardless of whether the VLR

regulator is running normally or shut down.

A ceramic capacitor of at least 1 µF with an ESR of no more than

250 mΩ should be fitted between the VLR terminal and GND to

guarantee stability and oscillation and voltage excursions beyond

the specified output voltage range. In some applications, the use

of redundant output capacitors may be advisable to avoid such a

condition in the event of a single-point capacitor high-impedance

failure.

PUMP REGULATOR

The gate drivers are powered by a programmable voltage internal

regulator which limits the supply to the drivers and therefore the

maximum gate voltage. At low input supply voltage, the regu-

lated supply is maintained by a charge pump boost converter

which requires a pump capacitor, typically 470 nF, connected

between the CP1 and CP2 terminals.

The regulated voltage, VREG, can be programmed to 8 or 11 V

and is available on the VREG terminal. The voltage level is

selected by the value of the VRG bit. When VRG = 1, the voltage

is set to 11 V; when VRG = 0, the voltage is set to 8 V. A suf-

ficiently large storage capacitor (see applications section) must

be connected to this terminal to provide the transient charging

current to the low side drivers and the bootstrap capacitors.

Operating Modes

The A4964 has two operating modes: SPI mode and stand-alone

mode. In SPI mode, it can be fully controlled by a small low-cost

external microcontroller through the serial interface. In stand-

alone mode, the LIN terminal becomes a PWM input that is used

to set the input demand. All configuration settings and basic con-

trol functions, except for the demand input, can be programmed

through the serial interface in both modes. The demand input can

only be set through the serial interface in the SPI mode.

SPI MODE

When operating in SPI mode (OPM = 0) the demand input is

determined by a 10-bit value, input from the external micro-

controller. The LIN terminal is a simple LIN physical interface

where the data on the LIN bus is interpreted and the responses are

provided by the external microcontroller. The only other function

that the LIN input provides is to wake the A4964 when it is in the

sleep state.

STAND-ALONE MODE

When operating in stand-alone mode (OPM = 1), the demand

input is only determined by the duty cycle of a PWM signal

applied to the LIN terminal. The 10-bit demand input through

the serial interface is not available in this mode. However, all

configuration settings and basic control functions, except for the

demand input, can still be programmed through the serial inter-

face. In this mode, the LIN input will also wake the A4964 when

it is in the sleep state.

LOW-POWER SLEEP STATE

The A4964 provides a low-power sleep state where the consump-

tion from the supply is reduced to a minimum by disabling all

normal operation including the charge pump regulator, the inter-

nal logic regulator, the external regulator, and the internal clock.

In the sleep state, the LIN terminal must be at the same voltage as

the supply terminal, VBB, and the IG terminal should be tied to

ground to achieve the minimum supply current.

There are two sleep states: the normal commanded sleep state

and the permanent sleep state. The permanent sleep state is only

entered following a watchdog cycle count failure. The state of the

A4964 is the same in both cases, but it will only exit the perma-

nent sleep state after a power off-on cycle as described in the

Microcontroller Watchdog section.

When operating in SPI mode (OPM = 0), the A4964 can only

be commanded to go into the normal sleep state using the serial

interface to change the GTS bit from 0 to 1 when the LIN input

is high (recessive). If the LIN input is low (dominant), any sleep

command through the serial interface will be ignored, and the

GTS bit must be changed to 0 followed by 1 to issue another go-

to-sleep command when the LIN input is high (recessive).When

operating in stand-alone mode (OPM = 1), the A4964 will go

into the normal sleep state using the serial interface to change the

GTS bit from 0 to 1, irrespective of the level on the LIN terminal.

In stand-alone mode, it will also go to sleep when the IG input

A4964 Datasheet(PDF) 24 Page - Allegro MicroSystems

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