A80603 datasheet(21/30 Pages) ALLEGRO

21 / 30 page

LED Driver with Pre-Emptive Boost

for Ultra-High Dimming Ratio and Low Output Ripple

A80603 and

A80603-1

Allegro MicroSystems, LLC

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

VDD

The VDD pin provides regulated bias supply for internal circuits.

Connect a CVDD capacitor with a value of 1 μF or greater to this

pin. The internal LDO can deliver up to 2 mA of current with a

typical VDD voltage of about 4.25 V. This allows it to serve as

the pull up voltage for FAULT pin.

Shutdown

If EN pin is pulled low for longer than tEN(OFF) (~16 ms), the

A80603 enters shutdown (sleep mode). The next time EN pin

goes high, all internal fault registers are cleared. The IC needs to

go through a complete soft start process after PWM goes high.

Figure 35: After EN = L for ~16 ms, the IC completely shuts down

so VDD (Blue) decays.

There is an alternative way to reset the internal fault status reg-

isters. By keeping EN = H and PWM = L for longer than 16 ms,

the A80603 clears all internal fault registers but does not go into

sleep mode. The next time PWM pin goes high, the IC will still

go through soft start process. The difference is that VDD voltage

and CLKOUT signal are always available as long as EN = H.

Figure 36: As long as EN = H, the IC does not shut down VDD and

CLKOUT. But internal latched faults are cleared by PWM = L for

~16 ms.

A80603 Datasheet(PDF) 21 Page - Allegro MicroSystems