ADP3168 datasheet(13/24 Pages) AD

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ADP3168

Rev. B | Page 13 of 24

APPLICATION INFORMATION

The design parameters for a typical Intel VRD 10 compliant

CPU application are as follows:

•

Input voltage (VIN) = 12 V

•

VID setting voltage (VVID) = 1.500 V

•

Duty cycle (D) = 0.125

•

Nominal output voltage at no load (VONL) = 1.480 V

•

Nominal output voltage at 65 A load (VOFL) = 1.3955 V

•

Static output voltage drop based on a 1.3 mΩ load line (RO)

from no load to full load

•

(VD) = VONL − VOFL = 1.480 V − 1.3955 V = 84.5 mV

•

Maximum output current (IO) = 65 A

•

Maximum output current step (∆IO) = 60 A

•

Number of phases (n) = 3

•

Switching frequency per phase (fSW) = 267 kHz

SETTING THE CLOCK FREQUENCY

The ADP3168 uses a fixed-frequency control architecture. The

frequency is set by an external timing resistor (RT). The clock

frequency and the number of phases determine the switching

frequency per phase, which relates directly to switching losses

and the sizes of the inductors and input and output capacitors.

With n = 3 for three phases, a clock frequency of 800 kHz sets

the switching frequency, fSW, of each phase to 267 kHz, which

represents a practical trade-off between the switching losses and

the sizes of the output filter components. Figure 3 shows that to

achieve an 800 kHz oscillator frequency, the correct value for RT

is 249 kΩ. Alternatively, the value for RT can be calculated using

()

Ω

−

(1)

where 5.83 pF and 1.5 MΩ are internal IC component values.

For good initial accuracy and frequency stability, a 1% resistor

is recommended.

SOFT START AND CURRENT LIMIT LATCH-OFF

DELAY TIMES

Because the soft-start and current limit latch-off delay functions

share the DELAY pin, these two parameters must be considered

together. The first step is to set CDLY for the soft-start ramp. This

ramp is generated with a 20 µA internal current source. The

value of RDLY has a second-order impact on the soft-start time

because it sinks part of the current source to ground. However,

as long as RDLY is kept greater than 200 kΩ, this effect is minor.

The value for CDLY can be approximated using

VID

DLY

VID

DLY

⎟

⎠

⎞

⎜

⎝

⎛

−

(2)

where tSS is the desired soft-start time. Assuming an RDLY of

390 kΩ and a desired a soft-start time of 3 ms, CDLY is 36 nF.

The closest standard value for CDLY is 39 nF. Once CDLY has been

chosen, RDLY can be calculated for the current-limit latch-off

time using

DLY

DELAY

DLY

(3)

If the result for RDLY is less than 200 kΩ, a smaller soft-start time

should be considered by recalculating the equation for CDLY, or a

longer latch-off time should be used. In no case should RDLY be

less than 200 k . In this example, a delay time of 8 ms gives

RDLY = 402 kΩ. The closest standard 5% value is 390 kΩ.

INDUCTOR SELECTION

The choice of inductance for the inductor determines the

ripple current in the inductor. Less inductance leads to more

ripple current, which increases the output ripple voltage and

conduction losses in the MOSFETs but allows using smaller

inductors and, for a specified peak-to-peak transient deviation,

less total output capacitance. Conversely, a higher inductance

means lower ripple current and reduced conduction losses but

requires larger inductors and more output capacitance for the

same peak-to-peak transient deviation. In any multiphase con-

verter, a practical value for the peak-to-peak inductor ripple

current is less than 50% of the maximum dc current in the

same inductor. Equation 4 shows the relationship between

the inductance, oscillator frequency, and peak-to-peak ripple

current in the inductor.

Equation 5 can be used to determine the minimum inductance

based on a given output ripple voltage.

(

)

VID

−

(4)

(

)

(

)

RIPPLE

VID

−

≥

(5)

Solving Equation 5 for a 10 mV p-p output ripple voltage yields:

(

)

456

kHz

267

375

Ω

−

≥

If the resulting ripple voltage is less than that designed for, the

inductor can be made smaller until the ripple value is met. This

allows optimal transient response and minimum output

decoupling.

The smallest possible inductor should be used to minimize the

number of output capacitors. Choosing a 600 nH inductor is a

good starting point and gives a calculated ripple current of

8.2 A. The inductor should not saturate at the peak current of

25.8 A and should be able to handle the sum of the power

dissipation caused by the average current of 22.7 A in the

winding and core loss.

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