ADSP-TS202S datasheet(21/40 Pages) AD

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ADSP-TS202S

Preliminary Technical Data

Rev. PrB

Page 21 of 40

December 2003

ADSP-TS202S—SPECIFICATIONS

Note that component specifications are subject to change with-

out notice. For information on Link port electrical

characteristics, see Link Port Low-Voltage, Differential-Signal

(LVDS) Electrical Characteristics and Timing on page 27.

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

Parameter

Test Conditions

Min

Typ

Max

Unit

VDD

Internal Supply Voltage

0.95

1.05

VDD_A

Analog Supply Voltage

0.95

1.05

VDD_IO

I/O Supply Voltage

2.38

2.63

VDD_DRAM

Internal DRAM Supply Voltage

1.425

1.575 V

TCASE

Case Operating Temperature

–40

+85

°C

VIH

High-Level Input Voltage

1 Applies to input and bidirectional pins.

@ VDD, VDD_IO = max

1.7

3.63

VIL

Low-Level Input Voltage1

@ VDD, VDD_IO = min

–0.5

0.8

IDD

VDD supply current for typical activity

2 For details on internal and external power calculation issues, see the EE-170, Estimating Power for the ADSP-TS201S on the Analog Devices website.

@ CCLK=500 MHz, VDD=1.0 V, TCASE=25ºC

2.39

IDD_A

VDD_A supply current for typical activity

@ CCLK=500 MHz, VDD=1.0 V, TCASE=25ºC

IDD_IO

VDD_IO supply current for typical activity

2 (DRAM

Internal Regulator Disabled)

@ SCLK=100 MHz, VDD_IO=2.5 V, TCASE=25ºC,

ENEDREG=0

0.16

IDD_DRAM

VDD_DRAM supply current for typical activity

@ CCLK=500 MHz, VDD_DRAM=1.5 V,

TCASE=25ºC, ENEDREG=0

0.40

VREF

Voltage reference

(VDD_IO ×0.56)

3 If the clock driver voltage is > 2.8 V and the clock driver voltage is used to generate SCLK_VREF, this formula becomes: (VCLOCK_DRIVE/2) ±5%)

SCLK_VREF

Voltage reference

(VDD_IO ×0.56)

Parameter

Test Conditions

Min

Max

Unit

VOH

High-Level Output Voltage

1 Applies to output and bidirectional pins.

@VDD_IO =min, IOH = –2 mA

2.18

VOL

Low-Level Output Voltage1

@VDD_IO =min, IOL =4 mA

0.4

IIH

High-Level Input Current

@VDD_IO =max, VIN =VDD_IO max

µA

IIH_PU

High-Level Input Current

@VDD_IO =max, VIN =VDD_IO max

µA

IIH_PD

High-Level Input Current

@VDD_IO =max, VIN =VDD_IO max

0.3

0.76

IIL

Low-Level Input Current

@VDD_IO =max, VIN =0V

µA

IIL_PU

Low-Level Input Current

@VDD_IO =max, VIN =0V

0.3

0.76

IIL_PU_AD

Low-Level Input Current

@VDD_IO =max, VIN = 0V

0.03

0.1

IOZH

Three-State Leakage Current High

@VDD_IO =max, VIN =VDD_IO max

µA

IOZH_PD

Three-State Leakage Current High

@VDD_IO =max, VIN =VDD_IO max

0.3

0.76

IOZL

Three-State Leakage Current Low

@VDD_IO =max, VIN =0V

µA

IOZL_PU

Three-State Leakage Current Low

@VDD_IO =max, VIN =0

0.3

0.76

IOZL_PU_AD

Three-State Leakage Current Low

@VDD_IO =max, VIN = 0

0.03

0.1

IOZL_OD

Three-State Leakage Current Low

@VDD_IO =max, VIN =0V

7.6

CIN

Input Capacitance2,3

2 Applies to all signals.

3 Guaranteed but not tested.

@fIN =1MHz,TCASE =25C, VIN =2.5V

Parameter name suffix conventions: no suffix = applies to pins without pullup or pull down resistors, _PD = applies to pin types (pd) or

(pd_0), _PU = applies to pin types (pu) or (pu_0), _PU_AD = applies to pin types (pu_ad), _OD = applies to pin types OD

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