IXFN100N50P

IXYS Reserves the Right to Change Limits, Test Conditions, and Dimensions.

Fig. 7. Input Admittance

0

20

40

60

80

100

120

140

160

4.04.5

5.05.5

6.06.5

7.0

7.5

25

- 40

Fig. 8. Transconductance

0

20

40

60

80

100

120

140

160

0

20

40

60

80

100

120

140

160

180

125

25

Fig. 9. Forward Voltage Drop of Intrinsic Diode

0

50

100

150

200

250

300

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

Fig. 10. Gate Charge

0

1

2

3

4

5

6

7

8

9

10

0

50

100

150

200

250

Fig. 11. Capacitance

100

1,000

10,000

100,000

0

5

10

15

20

25

30

35

40

f = 1 MHz

Ciss

Crss

Coss

Fig. 12. Forward-Bias Safe Operating Area

1

10

100

1000

10

100

1,000

Single Pulse

100μs

DC

10ms

1ms