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ADCMXL3021 Datasheet(PDF) 5 Page - Analog Devices

Part # ADCMXL3021
Description  Wide Bandwidth, Low Noise, Triaxial Vibration Sensor
PDF  50 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADCMXL3021 Datasheet(HTML) 5 Page - Analog Devices

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Data Sheet
ADcmXL3021
Rev. 0 | Page 5 of 50
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER SUPPLY VOLTAGE
Operating voltage range, VDD
3.0
3.3
3.6
V
Power Supply Current
Operating mode, VDD = 3.0 V
30.2
mA
Operating mode, VDD = 3.3 V
30.6
mA
Operating mode, VDD = 3.6 V
31.6
mA
Sleep mode, VDD = 3.0 V
1
mA
Sleep mode, VDD = 3.3 V
1.5
mA
Sleep mode, VDD = 3.6 V
2.3
mA
1 The maximum range depends on the frequency of vibration.
2 Endurance is qualified as per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
3 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22, Method A117. Retention lifetime depends on junction temperature.
TIMING SPECIFICATIONS
TC
= 25°C, VDD = 3.3 V, unless otherwise noted.
Table 2.
Normal Mode
RTS Mode
Parameter
Description
Min1
Typ
Max1
Min
Typ
Max1
Unit
fSCLK
SCLK frequency
0.01
14
12.5
14
MHz
tSTALL
Stall period between data bytes
16
N/A2
μs
tCLS
SCLK low period
38.5
38.5
ns
tCHS
SCLK high period
38.5
38.5
ns
t
CS
CS to SCLK edge
38.5
38.5
ns
tDAV
DOUT valid after SCLK edge
20
20
ns
tDSU
DIN setup time before SCLK rising edge
6
6
ns
tDHD
DIN hold time after SCLK rising edge
8
8
ns
tDSOE
CS assertion to DOUT active
20
0
20
ns
tHD
SCLK edge to DOUT invalid
20
20
ns
tSFS
Last SCLK edge to CS deassertion
38.5
38.5
ns
tRTS_BUSY
RTS mode only, data out valid burst
readout period end before BUSY rising
edge for next burst
N/A
5
μs
1 Guaranteed by design and characterization, but not tested in production.
2 N/A means not applicable. When using burst read mode, the stall period is not applicable.
Timing Diagrams
CS
SCLK
DOUT
DIN
1
2
3
4
5
6
15
16
R/W
A5
A6
A4
A3
A2
D2
MSB
DB14
D1
LSB
DB13
DB12
DB10
DB11
DB2
LSB
DB1
tCS
tSFS
tDAV
tHD
tCHS
tCLS
tDSOE
tDHD
tDSU
Figure 2. SPI Timing and Sequence



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