OPA325IDBVR datasheet(25/42 Pages) TI1

25 / 42 page

OPA325, OPA2325, OPA4325

www.ti.com

SBOS637D – OCTOBER 2016 – REVISED JUNE 2019

Product Folder Links: OPA325 OPA2325 OPA4325

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9 Power Supply Recommendations

The OPAx325 are specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V); many specifications apply from

–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or

temperature are presented in the Typical Characteristics section.

10 Layout

10.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

•

Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp

itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources

local to the analog circuitry.

–

Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close as possible to the device. A single bypass capacitor from V+ to ground is applicable for single-

supply applications.

•

Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective

methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.

A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Make sure

to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more

detailed information refer to, see Circuit Board Layout Techniques.

•

In order to reduce parasitic coupling, run the input traces as far away as possible from the supply or output

traces. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as

opposed to in parallel with the noisy trace.

•

Place the external components as close as possible to the device. As illustrated in Figure 57, keeping RF and

RG close to the inverting input minimizes parasitic capacitance.

•

Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit.

•

Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce

leakage currents from nearby traces that are at different potentials.

•

For best performance, clean the PCB following board assembly.

•

Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the

plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to

remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-

cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

OPA325IDBVR Datasheet(PDF) 25 Page - Texas Instruments

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