LT7101 datasheet(16/38 Pages) AD

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LT7101

Rev. 0

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between 0A and 1.11A. An internal 20μA pull-up on this

pin allows a single resistor to SGND to be used to set the

voltage. This pin can be floated to set the average output

current to 1.11A and the peak current limit to 1.64A.

By maintaining a fast and optimized current loop over all

operating conditions, the LT7101 responds to changes

in the ICTRL pin voltage with the greatest possible speed.

This is orders of magnitude faster than most competing

solutions, where a slow, average current loop is placed

outside of the voltage regulation loop. By placing the aver-

age current loop inside of the voltage regulation loop,

the LT7101 allows for current programming on a nearly

cycle-by-cycle basis.

The average output current can be monitored at the IMON

pin. The reconstructed inductor current signal (VSNS) is

run through a low pass filter (fc = 10kHz), buffered, and

then delivered to the IMON pin. The voltage on the IMON

normally varies between 0.4V and 1.3V, corresponding

to an average output current between 0A and 1.11A.

The IMON voltage may momentarily be less than 0.4V or

greater than 1.3V, but eventually is limited to these levels

by the average current loop. During SLEEP, this pin is held

at 0.4V.

Short-Circuit Protection and Minimum On-Time

The architecture of the LT7101 provides inherent protec-

tion against short-circuit conditions, without the need for

folding back either the output current or the oscillator

frequency. This is made possible because the PWM com-

parator is continuously receiving inductor current infor-

mation from the average current amplifier. This results in

automatic cycle skipping under short-circuit conditions

if the minimum on-time of the top switch is too long to

maintain control of the inductor current at the full switch-

ing frequency. Because a given switching cycle is skipped

only as needed to satisfy the high speed average current

loop, this creates a brick-wall style current limit without

any foldback or hiccups in the operation down to VOUT =

0V. Figure 2 illustrates the typical operation of this brick-

wall current limit.

Figure 2.

LOAD CURRENT (A)

7101 F02

1.5

0.5

Typical Current Limit Operation

While the average current loop is extremely fast, a failsafe

peak current limit (IPK) comparator has also been incor-

porated to ensure that the inductor current cannot exceed

a safe level even momentarily. The peak current limit is

internally set to 0.53A above the average current limit,

and tracks with the average current limit set by the volt-

age on the ICTRL pin. In practice, this peak current limit

comparator is only needed when there is an abnormal

voltage on the average current amplifier output filter and

a short-circuit is simultaneously applied. In this case, the

peak current limit comparator may be needed for a few

cycles while the average current amplifier filter settles.

When operating at a high step-down ratio from VIN to

VOUT, care should be taken to choose a switching fre-

quency that is low enough to avoid operation at minimum

on-time. However, in the event that a high step-down ratio

requires an on-time that is less than the minimum, the

LT7101 architecture offers inherent protection against

output overvoltage. Once again, the PWM comparator

will automatically cause the skipping of a cycle as needed

to maintain regulation of the output voltage. While this

avoids output overvoltage, operation in this mode is unde-

sirable as it increases inductor current ripple.

In addition to this inherent protection, a separate output

overvoltage comparator monitors the VFB voltage and pre-

vents top MOSFET turn-on if an overvoltage condition is

present (VFB exceeds VFB(OV)).

OPERATION

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