KMM372V413CS datasheet(6/19 Pages) SAMSUNG

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DRAM MODULE

KMM372V413CK/CS

NOTES

An initial pause of 200us is required after power-up followed

by any 8 RAS-only or CAS-before-RAS refresh cycles before

proper device operation is achieved.

Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are ref-

erence levels for measuring timing of input signals. Transition

times are measured between VIH(min) and VIL(max) and are

assumed to be 5ns for all inputs.

Measured with a load equivalent to 1TTL loads and 100pF.

Voh=2.0V and Vol=0.8V.

Operation within the

tRCD(max) limit insures that tRAC(max)

can be met.

tRCD(max) is specified as a reference point only.

tRCD is greater than the specified tRCD(max) limit, then

access time is controlled exclusively by

tCAC.

Assumes that

tRCD

≥tRCD(max).

This parameter defines the time at which the output achieves

the open circuit condition and is not referenced to VOH or VOL.

tWCS is not restrictive operating parameter. It included in the

data sheet as electrical characteristic only. If

tWCS

≥tWCS(min)

the cycle is an early write cycle and the data out pin will

remain high impedance for the duration of the cycle.

Either

tRCH or tRRH must be satisfied for a read cycle.

These parameters are referenced to the CAS leading edge in

early write cycles.

Operation within the

tRAD(max) limit insures that tRAC(max)

can be met.

tRAD(max) is specified as reference point only. If

tRAD is greater than the specified tRAD(max) limit, then access

time is controlled by

tAA.

The timing skew from the DRAM to the DIMM resulted from

the addition of buffers.

10.

11.

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