ST24E64EB3TR datasheet(8/16 Pages) STMICROELECTRONICS

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Write Operations

Following a START condition the master sends a

device select code with the RW bit reset to ’0’. The

ST24/25E64 acknowledge this and waits for 2

bytes of address. These 2 address bytes (8 bits

each) provide access to any of the 32 blocks of 256

bytes each. Writing in the ST24/25E64 may be

inhibited if input pin WC is taken high.

For the ST24/25E64 versions, any write command

with WC = ’1’ (during a period of time from the

START condition untill the end of the 2 Bytes

Address) will not modify data and will NOT be

acknowledged on data bytes, as in Figure 9.

Byte Write. In the Byte Write mode the master

sends one data byte, which is acknowledged by the

SCL

SDA

SCL

SDA

START

CONDITION

SDA

INPUT

SDA

CHANGE

AI00792

STOP

CONDITION

MSB

ACK

START

CONDITION

SCL

123

MSB

ACK

STOP

CONDITION

Figure 6. I2C Bus Protocol

ST24/25E64. The master then terminates the

transfer by generating a STOP condition.

Page Write. The Page Write mode allows up to 32

bytes to be written in a single write cycle, provided

that they are all located in the same row of 32 bytes

in the memory, that is the same Address bits (b12

to b5). The master sends one up to 32 bytes of data,

which are each acknowledged by the ST24/25E64.

After each byte is transfered, the internal byte

address counter (5 Least Significant Bits only) is

incremented. The transfer is terminated by the

master generating a STOP condition. Care must be

taken to avoid address counter ’roll-over’ which

could result in data being overwritten. Note that for

any write mode, the generation by the master of the

STOP condition starts the internal memory pro-

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ST24E64, ST25E64

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