STR720 datasheet(54/401 Pages) STMICROELECTRONICS

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STR720 - ENHANCED INTERRUPT CONTROLLER (EIC)

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Figure 8. Nested interrupt request sequence example

The IPR is a read/clear register, so writing a ‘0’ has no effect, while writing a ‘1’ reset the

related bit. Therefore refrain from using read-modify instructions to avoid corruption of the IPR

status.

Dynamic priority level modification: the main program and routines can be specifically

prioritized. Since CIPR is a read/write register, it is possible to modify dynamically the current

priority value during program execution. This means that a critical section can have a higher

priority with respect to other interrupt requests. A subsequent lowering of the priority is

allowed only down to the initial level of interrupt routine. Such initial priority level has been, of

course, conveniently stored inside the EIC hardware stack.

Note that it is likewise possible to even manipulate the Main Program execution priority.

Maximum depth of nesting: no more than 15 routines can be nested (one for each priority

level, from 1 to 15). If an interrupt routine at level N is being serviced, no other Interrupts

located at level N can interrupt it. This implies a maximum number of 16 nested levels

including the main program priority level.

Priority level 0: Interrupt requests at level 0, even if enabled, cannot be acknowledged, as

their priority cannot be strictly higher than the CIPR value. The pending bit in the IPR

(Interrupt Pending Register) is anyway set. Such a feature comes useful in a totally interrupt

polled environment.

The whole interrupting process is constituted by the following subsequent major steps:

INTERRUPT 0 HAS PRIORITY LEVEL 0

INTERRUPT 1 HAS PRIORITY LEVEL 1

INTERRUPT 2 HAS PRIORITY LEVEL 2

INTERRUPT 3 HAS PRIORITY LEVEL 3

INTERRUPT 4 HAS PRIORITY LEVEL 4

INTERRUPT 5 HAS PRIORITY LEVEL 5

INTERRUPT 6 HAS PRIORITY LEVEL 6

INTERRUPT 7 HAS PRIORITY LEVEL 7

INT. 1

INT. 5

INT. 2

PRIORITY LEVEL

MAIN PROGRAM

CPL set to 0

CPL = 1

INT. 5

CPL = 2

INT. 3

CPL = 3

CPL = 5

INT. 3

CPL = 3

INT. 4

CPL = 4

INT. 5

CPL = 5

INT. 7

CPL = 5

INT. 2

CPL = 2

CPL = 0

INT. 2

INT. 5

INT. 3

INT. 4

INT. 7

INT. 1

INT. 5

re-enable interrupt

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