STR720 datasheet(161/401 Pages) STMICROELECTRONICS

161 / 401 page

STR720 - ASYNCHRONOUS AHB-APB BRIDGE (A3BRG)

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This AHB/APB bridge is capable of addressing 13 peripherals. Each peripheral is connected

through an APB slave port to the APB bus and data size can be different from one peripheral

to the other. The APB memory mapping provides 4 kBytes memory space for each peripheral.

The Bridge is able to detect some errors while accessing to a peripheral:

■

an out of memory condition on the APB bus, when the address does not refer to a valid

peripheral. This could arise if the set of all peripheral’s memory spaces does not cover the

whole AHB mapping space

■

an access on the APB bus to a peripheral whose clock has been switched-off

■

an access on the APB bus to a peripheral which is currently under reset.

If one of the first 3 conditions occurs, the bridge does not start an APB transaction and reports

on the AHB bus an ERROR condition (if enabled). The type of error will be saved in the Bridge

Status Register and the address which has generated the error condition will be reported in

Figure 19. AHB/APB bridge block diagram

AHB

APB

resynchronization

stage

error management

configuration and

status registers

AHB Slave

APB master

per_clock[:] per_resetn[:]

STR720 Datasheet(PDF) 161 Page - STMicroelectronics