STR720 datasheet(182/401 Pages) STMICROELECTRONICS

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STR720 - UART

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ASCIntEnable

Address Offset: 10h

Reset value 0000h

The ASCIntEnable register enables a source of interrupt.

Interrupts will occur when a status bit in the ASCStatus register is 1, and the corresponding

bit in the ASCIntEnable register is 1.

Bit 15:9 = Reserved.

Write 0, will read back 0.

Bit 8 = ASCIntEnable[8]= RxHalfFullIE: Receiver buffer Half Full Interrupt Enable

0: interrupt disabled.

1: interrupt enabled.

Bit 7 = ASCIntEnable[7]=TimeoutIdleIE: Timeout Idle Interrupt Enable

0: interrupt disabled.

1: interrupt enabled.

Bit 6 = ASCIntEnable[6]=TimeoutNotEmpty IE: Timeout Not Empty Interrupt Enable

0: interrupt disabled.

1: interrupt enabled.

Bit 5 = ASCIntEnable[5]=OverrunErrorIE: Overrun Error Interrupt Enable

0: interrupt disabled.

1: interrupt enabled.

Bit 4 = ASCIntEnable[4]=FrameErrorIE: Framing Error Interrupt Enable

0: interrupt disabled.

1: interrupt enabled.

Bit 3 = ASCIntEnable[3]=ParityErrorIE: Parity Error Interrupt Enable

0: interrupt disabled.

1: interrupt enabled.

Bit 2 = ASCIntEnable[2]=TxHalfEmptyIE: Transmitter buffer Half Empty Interrupt Enable

0: interrupt disabled.

1: interrupt enabled.

Bit 1 = ASCIntEnable[1]=TxEmptyIE: Transmitter Empty Interrupt Enable

0: interrupt disabled.

1: interrupt enabled.

765432

RESERVED

ASCIntEnable

STR720 Datasheet(PDF) 182 Page - STMicroelectronics