STR720 datasheet(194/401 Pages) STMICROELECTRONICS

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STR720 - BUFFERED SPI (BSPI)

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17.4 Register description

BSPI Control/Status Register 1 (BSPCSR1)

Address Offset: 08h

Reset value: 0000h

Bits 15:12 = RFE[3:0]: Receive FIFO Enable.

The receive FIFO can be programmed to operate with a word depth up to 16. The receive

FIFO enable bits declare how many words deep the FIFO is for all transfers. The FIFO

defaults to one word deep, i.e. similar to a single data register. Table below shows how the

FIFO is controlled.

Bit 11:10 = WL[1:0]: Word Length.

These two bits configure the word length operation of the Receive FIFO and transmit data

registers as shown below:

765432

RFE[3:0]

WL[1:0]

CPHA

CPOL

BEIE

Reserved

REIE

RIE[1:0]

MSTR

BSPE

RFE[3:0]

Depth of FIFO

0000

1st word enabled

0001

1st & 2nd words enabled

0010

1-3 words enabled

0011

1-4 words enabled

0100

1-5 words enabled

0101

1-6 words enabled

0110

1-7 words enabled

0111

1-8 words enabled

1000

1-9 words enabled

1001

1-10 words enabled

1010

1-11 words enabled

1011

1-12 words enabled

1100

1-13 words enabled

1101

1-14 words enabled

1110

1-15 words enabled

1111

1-16 words enabled

WL[1:0]

Word Length

8-bit

16-bit

Reserved

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