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STR720 Datasheet(PDF) 398 Page - STMicroelectronics |
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STR720 Datasheet(HTML) 398 Page - STMicroelectronics |
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398 / 401 page  STR720 - ELECTRICAL CHARACTERISTICS 398/401 In figure 86 a sample of 4-beat burst read access is depicted, to show how access gets more efficient in the case of a burst read. The timing parameters of burst read access are the same of single read access. Figure 86. SDRAM Burst Read Access delay RAS-CAS latency CAS MICLK MIA[13:11] Bank MIA[10:0] Row Col0 MCS[x] MISA / RAS MIAA / CAS MID[32:0] Data0 MIWE Col1 Col2 Col3 Data1 Data2 Data3 Note: this diagram shows the timing with RAS-CAS delay, CAS latency set to 1 wait-state and no precharge delay. Activate Bank Read Precharge Bank Read Read Read |
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