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DS00001775B-page 3

MEC1633

Tool Requirements

For information on the latest version of the Metaware Development system, please see Application Note #26.14, “ARC

Metaware Development System.”

Description

The MEC1633 is the mixed signal base component of a multi-device advanced I/O controller architecture.

The

MEC1633 incorporates a high-performance 32-bit ARC 625D embedded microcontroller with a 192 Kilobyte Embedded

Flash Subsystem, 16 Kilobytes of SRAM, 1 Kilobyte EEPROM emulation, and a 2 Kilobyte EEPROM. The MEC1633

communicates with the system host using the Intel® Low Pin Count bus.

The MEC1633 is the EC Base Component of a split-architecture Advanced I/O Controller system which uses BC-Link

communication protocol to access up to three companion components. The BC-Link protocol is peer-to-peer providing

communication between the MEC1633 embedded controller and registers located in a companion.

The MEC1633 is directly powered by two separate suspend supply planes (VBAT and VTR) and senses a third runtime

power plane (VCC) to provide “instant on” and system power management functions. The MEC1633 also contains an

integrated VTR Reset Interface and a system Power Management Interface that supports low-power states and can

drive state changes as a result of hardware wake events as defined by the MEC1633 Wake Interface.

The MEC1633 defines a software development system interface that includes an MCU Serial Debug Port, a two pin

serial debug port with a 16C550A register interface that is accessible to the EC or to the LPC host and can operate up

to 2 MB/s, a flexible Flash programming interface, a Port 80 BIOS Debug Port, Gang Programmer Interface, and a JTAG

interface. The EC can also drive the JTAG interface as a master.

A top-level block diagram of the MEC1633 is shown in Figure 1.