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LTC6904HMS8 Datasheet(PDF) 10 Page - Linear Technology |
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LTC6904HMS8 Datasheet(HTML) 10 Page - Linear Technology |
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10 / 12 page ![]() LTC6903/LTC6904 10 69034fa generated by the slave lets the master know that the latest byte of information was received. The Acknowledge re- lated clock pulse is generated by the master. The master releases the SDA line (HIGH) during the Acknowledge clock pulse. The slave-receiver must pull down the SDA line during the Acknowledge clock pulse so that it remains a stable LOW during the HIGH period of this clock pulse. Write Word Protocol The master initiates communication with the LTC6904 with a START condition and a 7-bit address followed by the Write Bit (Wr) = 0. The LTC6904 acknowledges and the master delivers the most significant data byte. Again the LTC6904 acknowledges and the data is latched into the most significant data byte input register. The master then delivers the least significant data byte. The LTC6904 acknowledges once more and latches the data into the least significant data byte input register. Lastly, the master terminates the communication with a STOP condition. Slave Address The LTC6904 can respond to one of two 7-bit addresses. The first 6 bits (MSBs) have been factory programmed to 001011. The address pin, ADR (Pin 4) is programmed by the user and determines the LSB of the slave address, as shown in the table below: ADR (Pin 4) LTC6904 Address 0 0010111 1 0010110 TYPICAL APPLICATIO S Write Word Protocol Used by the LTC6904 Slave Address A Wr MS Data Byte A LS Data Byte A P S 71 18 1 8 6903 AI01 11 1 S = Start Condition, Wr = Write Bit = 0, A = Acknowledge, P = Stop Condition LTC6904 I2C Interface The LTC6904 communicates with a host (master) using the standard I2C 2-wire interface. The Timing Diagram shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 SMBus Accelerator, are required on these lines. If the I2C interface is not driven with a standard I2C compatible device, care must be taken to ensure that the SDA line is released during the ACK cycle to prevent bus contention. The LTC6904 is a receive-only (slave) device. The master can communicate with the LTC6904 using the Write Word protocols as explained later. The START and STOP Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a communi- cation to a slave device by transmitting a START condi- tion. A START condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition. A STOP condition is generated by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another SMBus device. Acknowledge The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active LOW) |
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