PIC18F8490 datasheet(3/10 Pages) MICROCHIP

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DS80207B-page 3

PIC18F6390/6490/8390/8490

Module: CCP

When operating either Timer1 or Timer3 as a

counter with a prescale value other than 1:1 and

operating the CCP in Compare mode with the

Special

Event

Trigger

(CCP1CON

bits

CCP1M3:CCP1M0 = 1011), the Special Event

Trigger Reset of the timer occurs as soon as there

match

between

TMRxH:TMRxL

and

CCPR1H:CCPR1L.

This differs from the PIC18F452, where the Special

Event Trigger Reset of the timer occurs on the next

prescaler output pulse after the match between

TMRxH:TMRxL and CCPR1H:CCPR1L.

Work around

To achieve the same timer Reset period on the

PIC18F8490 family as the PIC18F452 family for a

given clock source, add 1 to the value in

CCPR1H:CCPR1L.

other

words,

CCPR1H:CCPR1L = x for the PIC18F452, to

achieve

the

same

Reset

period

the

PIC18F8490 family, CCPR1H:CCPR1L = x + 1,

where the prescale is 1, 2, 4 or 8 depending on the

T1CKPS1:T1CKPS0 bit values.

Date Codes that pertain to this issue:

All engineering and production devices.

Module: CCP

The CCP1 and CCP2, configured for PWM mode

with 1:1 Timer2 prescaler and duty cycle set to the

period minus 1, may result in the PWM output(s)

remaining at a logic low level.

Clearing the PR2 register to select the fastest

period may also result in the output(s) remaining at

a logic low output level.

Work around

To ensure a reliable waveform, verify that the

selected duty cycle does not equal the 10-bit

period minus 1 prior to writing these locations, or

use 1:4 or 1:16 Timer2 prescale. Also, verify the

PR2 register is not written to 00h.

All other duty cycle and period settings will function

as described in the Device Data Sheet.

The CCP modules remain capable of 10-bit

accuracy.

Date Codes that pertain to this issue:

All engineering and production devices.

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