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DP83821 Datasheet(PDF) 48 Page - National Semiconductor (TI) |
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DP83821 Datasheet(HTML) 48 Page - National Semiconductor (TI) |
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48 / 86 page  48 www.national.com 4.0 Register Set (Continued) 4.2.7 Interrupt Mask Register This register masks the interrupts that can be generated from the ISR. Writing a “1” to the bit enables the corresponding interrupt. During a hardware reset, all mask bits are cleared. Setting a mask bit allows the corresponding bit in the ISR to cause an interrupt. ISR bits are always set to 1, however, if the condition is present, regardless of the state of the corresponding mask bit. Tag: IMR Size: 32 bits Hard Reset: 00000000h Offset: 0014h Access: Read Write Soft Reset: 00000000h bit tag description usage 31 unused 30 TXDESC3 Tx Descriptor for Priority Queue 3 When this bit is 3, the corresponding bit in the ISR will not cause an interrupt. 29 TXDESC2 Tx Descriptor for Priority Queue 2 When this bit is 2, the corresponding bit in the ISR will not cause an interrupt. 28 TXDESC1 Tx Descriptor for Priority Queue 1 When this bit is 1, the corresponding bit in the ISR will not cause an interrupt. 27 TXDESC0 Tx Descriptor for Priority Queue 0 When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 26 RXDESC3 Rx Descriptor for Priority Queue 3 When this bit is 3, the corresponding bit in the ISR will not cause an interrupt. 25 RXDESC2 Rx Descriptor for Priority Queue 2 When this bit is 2, the corresponding bit in the ISR will not cause an interrupt. 24 RXDESC1 Rx Descriptor for Priority Queue 1 When this bit is 1, the corresponding bit in the ISR will not cause an interrupt. 23 RXDESC0 Rx Descriptor for Priority Queue 0 When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 22 TXRCMP Transmit Reset Complete When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 21 RXRCMP Receive Reset Complete When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 20 DPERR Detected Parity Error When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 19 SSERR Signaled System Error When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 18 RMABT Received Master Abort When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 17 RTABT Received Target Abort When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 16 RXSOVR Rx Status FIFO Overrun When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 15 HIBINT High Bits Interrupt When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 14 PHY Phy interrupt When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 13 PME Power Management Event When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 12 SWI Software Interrupt When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 11 MIB MIB Service When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 10 TXURN Tx Underrun When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 9 TXIDLE Tx Idle When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 8 TXERR Tx Packet Error When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 7 TXDESC Tx Descriptor When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 6 TXOK Tx Packet OK When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 5 RXORN Rx Overrun When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 4 RXIDLE Rx Idle When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 3 RXEARLY Rx Early Threshold When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 2 RXERR Rx Packet Error When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 1 RXDESC Rx Descriptor When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. 0 RXOK Rx OK When this bit is 0, the corresponding bit in the ISR will not cause an interrupt. |
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