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ABV2005QC Datasheet(PDF) 1 Page - Abracon Corporation

Part # ABV2005QC
Description  Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
PDF  8 Pages
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Manufacturer  ABRACON [Abracon Corporation]
Direct Link  https://abracon.com
Logo ABRACON - Abracon Corporation

ABV2005QC Datasheet(HTML) 1 Page - Abracon Corporation

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ABV2005/-06/-07/-08/-09
Low Phase Noise VCXO with multipliers (for 100-200MHz Fund Xtal)
30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546-8001 www.Abracon.com 03/21/05 Page 1
FEATURES
• 100MHz to 200MHz Fundamental Mode Crystal.
• Output range: 100 – 200MHz (no multiplication),
200 – 400MHz (2x multiplier), 400 – 800MHz (4x
multiplier), or 800MHz – 1GHz (ABV2009
TSSOP only, 8x multiplier).
• High yield design supports up to 2pF stray
capacitance at 200MHz.
• CMOS (Standard drive ABV2007 or Selectable
Drive ABV2006), PECL (Enable low ABV2008 or
Enable high ABV2005) or LVDS output
(ABV2009).
• Integrated variable capacitors.
• Supports 3.3V-Power Supply.
• Available in 16-Pin (TSSOP or 3x3mm QFN)
Note: ABV2006 only available in 3x3mm.
Note: ABV2007 only available in TSSOP.
DESCRIPTION
The ABV2005/-06/-07/-08/-09 is a family of VCXO
ICs specifically designed to pull high frequency
fundamental crystals. Their design was optimized to
tolerate higher limits of interelectrode capacitance
and bonding capacitance to improve yield. They
achieve very low current into the crystal resulting in
better overall stability. Their internal varicaps allow
an on chip frequency pulling, controlled by the
VCON input.
BLOCK DIAGRAM
PIN CONFIGURATION
(Top View)
^: Internal pull-up
*: ABV2006 pin 12 is output drive select (DRIVSEL)
(0 for High Drive CMOS, 1 for Standard Drive CMOS)
OUTPUT ENABLE LOGICAL LEVELS
Part #
OE
State
0 (Default)
Output enabled
ABV2008
1
Tri-state
0
Tri-state
ABV2005
ABV2006
ABV2007
ABV2009
1 (Default)
Output enabled
OE input: Logical states defined by PECL levels for ABV2008
Logical states defined by CMOS levels for ABV2005/-06/-
07/-09
XIN
XOUT
OE
Q
VCON
Q
PLL by-pass
SEL
PLL
(Phase
Locked
Loop)
Oscillator
Amplifier
w/
integrated
varicaps
1
2
3
4
5
6
7
8
VDD
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
XIN
XOUT
SEL3^
SEL2^
OE
VCON
GND
SEL0^
SEL1^
GND
CLKC
VDD
CLKT
GND
GND
ABV200x
GND
VDD
CLKT
CLKC
XOUT
XIN
SEL2^
OE
4
16
15
14
13
12
11
10
9
8
7
6
5
12
3


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