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LPC47M14X Datasheet(PDF) 125 Page - SMSC Corporation

Part # LPC47M14X
Description  128 PIN ENGANCED SUPER I/O CONTROLLER WITH AN LPC INTERFACE AND USB HUB
PDF  205 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

LPC47M14X Datasheet(HTML) 125 Page - SMSC Corporation

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SMSC DS – LPC47M14X
Page 125
Rev. 03/19/2001
7
RUNTIME REGISTERS
The following registers are runtime registers in the LPC47M14x. They are located at the address programmed in the
Base I/O Address in Logical Device A (also referred to as the PME register) at the offset shown. These registers are
powered by VTR.
Table 58 – Runtime Register Block Summary
REGISTER
OFFSET
(hex)
TYPE
HARD
RESET
VCC POR
VTR POR
SOFT
RESET
REGISTER
00
R/W
-
-
0x00
-
PME_STS
01
R
-
-
-
-
Reserved – reads return 0
02
R/W
-
-
0x00
-
PME_EN
03
R
-
-
-
-
Reserved – reads return 0
04
R/W
-
-
0x00
-
PME_STS1
05
R/W
-
-
0x00
-
PME_STS2
06
R/W
-
-
0x00
-
PME_STS3
07
R/W
-
-
0x00 (Note 5)
-
PME_STS4
08
R/W
-
-
0x00 (Note 5)
-
PME_STS5
09
R
-
-
-
-
Reserved – reads return 0
0A
R/W
-
-
0x00
-
PME_EN1
0B
R/W
-
-
0x00
-
PME_EN2
0C
R/W
-
-
0x00
-
PME_EN3
0D
R/W
-
-
0x00
-
PME_EN4
0E
R/W
-
-
0x00
-
PME_EN5
0F
R
-
-
-
-
Reserved – reads return 0
10
R/W
Note 4
Note 4
0x02 (Note 4)
(Note 4)
SMI_STS 1
11
R/W
-
-
0x00
-
SMI_STS 2
12
R/W
-
-
0x00
-
SMI_STS3
13
R/W
-
-
0x00 (Note 5)
-
SMI_STS4
14
R/W
-
-
0x00
-
SMI_STS5
15
R
-
-
-
-
Reserved – reads return 0
16
R/W
-
-
0x00
-
SMI_EN1
17
R/W
-
-
0x00
-
SMI_EN2
18
R/W
-
-
0x00
-
SMI_EN3
19
R/W
-
-
0x00
-
SMI_EN4
1A
R/W
-
-
0x00
-
SMI_EN5
1B
R
-
-
-
-
Reserved – reads return 0
1C
R/W
-
-
0x00
-
MSC_STS
1D
R
-
-
-
-
Reserved – reads return 0
1E
R/W
0x01
0x01
-
-
Force Disk Change
1F
R
-
-
-
-
Floppy Data Rate Select Shadow
20
R
-
-
-
-
UART1 FIFO Control Shadow
21
R
-
-
-
-
UART2 FIFO Control Shadow
22
R/W
(Note 1)
-
-
0x00
-
Device Disable Register
23
R/W
-
-
0x01
-
GP10
24
R/W
-
-
0x01
-
GP11
25
R/W
-
-
0x01
-
GP12
26
R/W
-
-
0x01
-
GP13
27
R/W
-
-
0x01
-
GP14
28
R/W
-
-
0x01
-
GP15



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