LPC47M14X datasheet(127/205 Pages) SMSC

127 / 205 page

SMSC DS – LPC47M14X

Page 127

Rev. 03/19/2001

OFFSET

(hex)

TYPE

HARD

RESET

VCC POR

VTR POR

SOFT

RESET

0x00

Fan2 Tachometer Register

R/W

0x00

Fan1 Preload Register

R/W

0x00

Fan2 Preload Register

R/W

0x00

LED1

R/W

0x00

LED2

R/W

0x00

Keyboard Scan Code

60-7F

Reserved – reads return 0

Note 1: This register is read-only when GP43 register bit [3:2] = 01 and the GP43 pin is high.

Note 2: Bits [3:2] of this register are reset (cleared) on VCC POR and Hard Reset (and VTR POR).

Note 3: Bit 3 of this register is reset (cleared) on VCC POR and Hard Reset (and VTR POR).

Note 4: The parallel port interrupt defaults to 1 when the parallel port activate bit is cleared.

Note 5: Bits 2 and 3 of the PME_STS4 and SMI_STS4 registers, and bit 3 of the PME_STS5 register may be set on a

VCC POR. If GP32, GP33 and GP53 are configured as input, then their corresponding PME and SMI status bits will be

set on a VCC POR Also, GP32 and GP33 pins revert to their non-inverting GPIO input function when VCC is removed

from the part. These GPIOs cannot be used for PME wakeup when the part is under VTR power (VCC=0).

The following registers are located at an offset from (PME_BLK) the address programmed into the base I/O address

Table 59 – PME, SMI, GPIO, FAN Register Description

NAME

REG OFFSET

(hex)

DESCRIPTION

PME_STS

Default = 0x00

on VTR POR

(R/W)

Bit[0] PME_Status

= 0 (default)

= 1 Set when LPC47M14x would normally assert the

nIO_PME signal, independent of the state of the

PME_En bit.

Bit[7:1] Reserved

PME_Status is not affected by Vcc POR, SOFT RESET

or HARD RESET.

Writing a “1” to PME_Status will clear it and cause the

LPC47M14x to stop asserting nIO_PME, in enabled.

Writing a “0” to PME_Status has no effect.

N/A

(R)

Reserved – reads return 0

PME_EN

Default = 0x00

on VTR POR

(R/W)

Bit[0] PME_En

= 0

nIO_PME signal assertion is disabled (default)

= 1

Enables LPC47M14x to assert nIO_PME signal

Bit[7:1] Reserved

PME_En is not affected by Vcc POR, SOFT RESET or

HARD RESET

N/A

(R)

Reserved – reads return 0

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