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L9468 Datasheet(PDF) 5 Page - STMicroelectronics |
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L9468 Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 8 page ![]() 5/8 L9468 3FAULT The following table lists the conditions that cause the fault lamp driver to function. To prevent lamp flicker, spe- cific faults are required to be present for TDELAY seconds before the lamp driver is activated. This delay is indicated in the table. Table 7. Table 8. Regulation Features Notes: 6. Lamp and Ignition are cooperative. Either can turn on the device when the other is left open or held low. When both go below their minimum thresholds the L9468 goes into "L" Terminal Control (LTC). The L9468 will remain in LTC until the phase (P) voltage drops below VP2 and the frequency drops below fIRF at the VP1 threshold then the L9468 is disabled. 7. This threshold on the phase signal is used to detect the phase frequency, fIFR, for the Initiation of field regulation. 8. This threshold on the phase signal is used to sense the presence of the phase for fault detection purposes. 9. This is the time duration the L9468 takes to rump up from 0 % to 100% duty cycle in response to an increased load on the enerator. The LRC ratio is set 1:4 and the Vreg comparator status is latched at foundamental frequency rate. 10. Cut-back occurs when both the "L" and "I" terminals are LOW . If the "I" terminal is disconnected it will assume a logic LOW allowing the "L" terminal to perform the function alone. In cut-back, to prevent the loss of phase signal, a 31.25% duty cycle is applied to field output when phase drops below Vp2 Conditions Delay 1. Key-on (wiring check), lamp stays on for 1 ± 0.15 sec regardless other conditions No 2. VGO / S> VOV Yes 3. VGO / S < undervoltage threshold voltage AND Phase frequency > fLRC Yes 4. Phase Voltage < VP2 AND VGO / S < setpoint Yes 5. Phase frequency < fIFR Yes 6. No connection between Battery and VGO No 7. FAILSAFE Yes Symbol Parameter Test Condition Min. Typ. Max. Unit VLON Lamp term turn on threshold 6 0.8 1 1.15 V ILON Lamp term current sensitivity VL = 1 V to Vsp 0.09 0.78 mA VP1 Initiation of regulation detection phase voltage threshold 7 IP = 1mA (sinking current) 2.5 3 3.5 V VP2 Fault detection phase voltage threshold 8 7 89V IP Sinking current @ P terminal VP = 1.5V 0.5 1 1.8 mA fIFR Initiation of field regulation frequency 53.04 61 70.15 Hz FSDF Field Strobe Duty Factor @ "power up" with fPHASE < fIFR 31.25 % LRC Load Response Control rate 9 2.125 2.5 2.875 s fLRC LRC transition frequency LRC is enabled below this value 263.5 310 356.5 Hz VLCB "L" term. Cut-Back Setpoint "L" = 0V, "I" = 0V 10 VS- 20% VS- 25% VS-30% V |
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