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74V1T77 Datasheet(PDF) 1 Page - STMicroelectronics |
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74V1T77 Datasheet(HTML) 1 Page - STMicroelectronics |
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1 / 10 page  1/10 July 2001 s HIGH SPEED: tPD = 4.7ns (TYP.) at VCC = 5V s LOW POWER DISSIPATION: ICC = 1µA(MAX.) at TA=25°C s COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN), VIL = 0.8V (MAX) s POWER DOWN PROTECTION ON INPUTS s SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8mA (MIN) at VCC = 4.5V s BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL s OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V s IMPROVED LATCH-UP IMMUNITY DESCRIPTION The 74V1T77 is an advanced high-speed CMOS SINGLE D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is designed to operate from 4.5V to 5.5V, making this device ideal for portable applications. The single D-Type latch is controlled by an Latch Enable Input (LE). While the LE input is held at a high level, the Q output will follow the data input precisely. When the LE input is taken low the Q output is latched precisely at the logic level of D data input. Power down protection is provided on inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. It’s available in the commercial and extended temperature range. All inputs and output are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. 74V1T77 SINGLE D-TYPE LATCH PIN CONNECTION AND IEC LOGIC SYMBOLS ORDER CODES PACKAGE T & R SOT23-5L 74V1T77STR SOT323-5L 74V1T77CTR SOT323-5L SOT23-5L |
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Similar Description - 74V1T77 |
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