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74LVC3G16 Datasheet(PDF) 1 Page - Nexperia B.V. All rights reserved |
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74LVC3G16 Datasheet(HTML) 1 Page - Nexperia B.V. All rights reserved |
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1 / 15 page ![]() 1. General description The 74LVC3G16 provides three buffers. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of the 74LVC3G16 as a translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 24 mA output drive (V CC =3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Multiple package options Specified from 40 C to +85 C and 40 C to +125 C 74LVC3G16 Triple buffer Rev. 2 — 11 October 2016 Product data sheet |
Similar Part No. - 74LVC3G16 |
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Similar Description - 74LVC3G16 |
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