LPC47M112 datasheet(21/208 Pages) SMSC

21 / 208 page

Enhanced Super I/O Controller with LPC Interface

Datasheet

SMSC DS – LPC47M112

Page 21

Rev. 02/02/2005

DATASHEET

FUNCTIONAL DESCRIPTION

8.1 Super I/O Registers

The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately

after power up. The base addresses of the FDC, serial and parallel ports, PME register block, Game port and

configuration register block can be moved via the configuration registers. Some addresses are used to access more

than one register.

8.2 Host Processor Interface (LPC)

The host processor communicates with the LPC47M112 through a series of read/write registers via the LPC interface.

The port addresses for these registers are shown in Table 1. Register access is accomplished through I/O cycles or

DMA transfers. All registers are 8 bits wide.

Table 1 - Super I/O Block Addresses

ADDRESS

BLOCK NAME

LOGICAL DEVICE

Base+(0-5) and +(7)

Floppy Disk

Base+(0-7)

Serial Port Com 1

Base1+(0-7)

Base2+(0-7)

Serial Port Com 2

Base+(0-3)

Base+(0-7)

Base+(0-3), +(400-402)

Base+(0-7), +(400-402)

Parallel Port

SPP

EPP

ECP

ECP+EPP+SPP

60, 64

KYBD

Base + 0

Game Port

Base + (0-5F)

Runtime Registers

Base + (0-7)

MPU-401

Base + (0-1)

Configuration

Note:

Refer to the configuration register descriptions for setting the base address.

8.3 LPC INTERFACE

The following sub-sections specify the implementation of the LPC bus.

8.3.1

LPC INTERFACE SIGNAL DEFINITION

The signals required for the LPC bus interface are described in the table below. LPC bus signals use PCI 33MHz

electrical signal characteristics.

SIGNAL NAME

TYPE

DESCRIPTION

LAD[3:0]

I/O

LPC address/data bus. Multiplexed command, address and data bus.

nLFRAME

Input

Frame signal. Indicates start of new cycle and termination of broken

cycle

nPCI_RESET

Input

PCI Reset.

Used as LPC Interface Reset. Same functionality as

RST_DRV but active low 3.3V.

nLDRQ

Output

Encoded DMA/Bus Master request for the LPC interface.

nIO_PME

Power Mgt Event signal. Allows the LPC47M112 to request wakeup.

nLPCPD

Input

Powerdown Signal. Indicates that the LPC47M112 should prepare for

power to be shut on the LPC interface.

SER_IRQ

I/O

Serial IRQ.

LPC47M112 Datasheet(PDF) 21 Page - SMSC Corporation

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