DAS6001HA2B-T datasheet(4/26 Pages) MICROCHIP

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DSA60XX

DS20006221A-page 4

 2019 Microchip Technology Inc.

Output Transition Time

Rise Time/Fall Time

tRX/tFX

—

2.5

3.5

DSC60x3B

Low Drive,

20% to 80%

CL = 5 pF

VDD = 1.8V

—

1.5

2.2

VDD =

2.5V/3.3V

tRY/tFY

—

1.2

2.0

DSC60x1B

Std. Drive,

20% to 80%

CL = 10 pF

VDD = 1.8V

—

0.6

1.2

VDD =

2.5V/3.3V

Output Duty Cycle Note 8

SYM

—

Period Jitter, RMS

JPER

—

DSC60x3B

Low Drive,

FOUT =

27 MHz

CL = 5 pF

VDD = 1.8V

—

VDD =

2.5V/3.3V

—

DSC60x1B

Std. Drive,

FOUT =

27 MHz

CL = 10 pF

VDD = 1.8V

—

VDD =

2.5V/3.3V

Cycle-to-Cycle Jitter, Peak

JCy–Cy

—

120

—

DSC60x3B

Low Drive,

FOUT =

27 MHz

CL = 5 pF

VDD = 1.8V

—

VDD =

2.5V/3.3V

—

115

—

DSC60x1B

Std. Drive,

FOUT =

27 MHz

CL = 10 pF

VDD = 1.8V

—

VDD =

2.5V/3.3V

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Characteristics: Unless otherwise indicated, VDD = 1.8V –5% to 3.3V +10%, TA = –40°C to +125°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Note 1: Pin 4 VDD should be filtered with 0.1 μF capacitor.

2: Not including current through pull-up resistor on EN pin (if configured).

3: Includes frequency variations due to initial tolerance, temp. and power supply voltage.

4: Input waveform must be monotonic with rise/fall time < 10 ms

5: Output Disable time takes up to two periods of the output waveform + 200 ns.

6: For parts configured with OE, not Standby.

7: Output is enabled if pad is floated or not connected.

8: Output Duty Cycle will be 40% to 60% when output frequency is between 40 MHz to 60 MHz.

9: Time to reach 90% of target VDD. Power ramp rise must be monotonic.

10: Peak-to-peak period jitter is measured over 10,000 cycles.

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