K6R1016V1D-EC08SLASH10 datasheet(3/9 Pages) SAMSUNG

3 / 9 page

PRELIMINARY

Rev. 3.0

- 3 -

July 2004

PRELIMINARY

K6R1004V1D

CMOS SRAM

for AT&T

256K x 4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating)

GENERAL DESCRIPTION

FEATURES

• Fast Access Time 8,10ns(Max.)

• Low Power Dissipation

Standby (TTL)

: 20mA(Max.)

(CMOS) : 5mA(Max.)

Operating

//K6R1004V1D-08: 80mA(Max.)

K6R1004V1D-10: 65mA(Max.)

•

Single 3.3

±0.3V Power Supply

• TTL Compatible Inputs and Outputs

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• Center Power/Ground Pin Configuration

• Standard Pin Configuration :

K6R1004V1D-J : 32-SOJ-400

K6R1004V1D-K : 32-SOJ-400 (Lead-Free)

• Operating in Commercial and Industrial Temperature range.

The K6R1004V1D is a 1,048,576-bit high-speed Static Random

Access Memory organized as 262,144 words by 4 bits.

The K6R1004V1D uses 4 common input and output lines and

has an output enable pin which operates faster than address

access time at read cycle. The device is fabricated using

SAMSUNG

′s advanced CMOS process and designed for

high-speed circuit technology. It is particularly well suited for

use in high-density high-speed system applications. The

K6R1004V1D is packaged in a 400 mil 32-pin plastic SOJ.

PIN FUNCTION

Pin Name

Pin Function

A0 - A17

Address Inputs

Write Enable

Chip Select

Output Enable

I/O1 ~ I/O4

Data Inputs/Outputs

VCC

Power(+3.3V)

VSS

Ground

N.C

No Connection

PIN CONFIGURATION(Top View)

Clk Gen.

I/O1 ~ I/O4

FUNCTIONAL BLOCK DIAGRAM

Data

Cont.

Column Select

CLK

Gen.

Pre-Charge Circuit

Memory Array

512 Rows

512x4 Columns

I/O Circuit &

SOJ

A17

A16

A15

A14

A13

I/O4

Vss

Vcc

I/O3

A12

A11

A10

N.C

I/O1

Vcc

Vss

I/O2

N.C

A10 A11 A12 A13 A14 A15

A16 A17

K6R1016V1D-EC08/10 Datasheet(PDF) 3 Page - Samsung semiconductor

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