DS3254 datasheet(45/71 Pages) DALLAS

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Table 17-C. Framer Interface Timing

(VDD = 3.3V

±5%, TA = -40°C to +85°C.) (Figure 17-1 and Figure 17-2)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

(Note 1)

22.4

(Note 2)

29.1

RCLK/TCLK Clock Period

(Note 3)

19.3

RCLK Duty Cycle

t2/t1, t3/t1

(Notes 4, 5)

TCLK Duty Cycle

t2/t1, t3/t1

(Note 5)

MCLK Duty Cycle

t2/t1, t3/t1

(Note 5)

TPOS/TDAT, TNEG to TCLK Setup

Time

(Notes 5, 6)

TPOS/TDAT, TNEG Hold Time

(Notes 5, 6)

RCLK to RPOS/RDAT, RNEG/RLCV,

and PRBS Value Change

(Notes 4, 5, 7)

RCLK Rise and Fall Time

(Notes 5, 8)

TCLK Rise and Fall Time

(Notes 5, 9)

Note 1:

DS3 mode.

Note 2:

E3 mode.

Note 3:

STS-1 mode.

Note 4:

Outputs loaded with 25pF, measured at 50% threshold.

Note 5:

Not tested during production test.

Note 6:

When TCINV = 0, TPOS/TDAT and TNEG are sampled on the rising edge of TCLK. When TCINV = 1, TPOS/TDAT and TNEG

are sampled on the falling edge of TCLK.

Note 7:

When RCINV = 0, RPOS/RDAT and RNEG/RLCV are updated on the falling edge of RCLK. When RCINV = 1, RPOS/RDAT and

RNEG/RLCV are updated on the rising edge of RCLK.

Note 8:

Outputs loaded with 25pF, measured between VOL (max) and VOH (min).

Note 9:

Measured between VIL (max) and VIH (min).

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