CYM9260
CYM9261B
CYM9262A
CYM9263
Document #: 38-05002 Rev. **
Page 7 of 12
AC Test Loads and Waveforms[3]
3.3V
GND
90%
10%
90%
10%
≤ 3ns
≤ 3 ns
OUTPUT
R1
R2
5pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
ALL INPUT PULSES
OUTPUT
RL = 50 Ω
VL =1.5V
VCCQ
[2]
Switching Characteristics Over the Operating Range
Parameter
Description
CYM9260/61/62/63
66 MHz
50 MHz
Min.
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
15
20
ns
tCH
Clock HIGH
6
8
ns
tCL
Clock LOW
6
8
ns
tAS
Address Set-Up Before CLK Rise
3.1
3.1
ns
tAH
Address Hold After CLK Rise
0.5
0.5
ns
tCDV
Data Output Valid After CLK Rise
10.3
14
ns
tDOH
Data Output Hold After CLK Rise
3
3
ns
tADS
ADSP, ADSC Set-Up Before CLK Rise
3.1
3.1
ns
tADSH
ADSP, ADSC Hold After CLK Rise
0. 5
0.5
ns
tWES
WH, WL Set-Up Before CLK Rise
3.1
3.1
ns
tWEH
WH, WL Hold After CLK Rise
0.5
0.5
ns
tDS
Data Input Set-Up Before CLK Rise
3.3
3.3
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
ns
tCSS
Chip Select Set-Up
3.1
3.1
ns
tCSH
Chip Select Hold After CLK Rise
0.5
0.5
ns
tEOZ
OE HIGH to Output High Z[4]
77
ns
tEOV
OE LOW to Output Valid
7
7
ns
Notes:
2.
Resistor values for VCCQ = 3.3V are R1 = 317Ω and R2 = 351 Ω.
3.
Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads. All measurements are made at room temperature.
4.
tEOZ is specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage.
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