LTC2439-1IGN datasheet(10/28 Pages) LINER

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LTC2439-1

24391f

Table 1. Channel Selection

MUX ADDRESS

CHANNEL SELECTION

ODD/

SGL

SIGN

A2 A1 A0

123456789

COM

000

IN+

IN–

000

IN+

IN–

000

IN+

IN–

000

IN+

IN–

001

IN+

IN–

001

IN+

IN–

001

IN+

IN–

001

IN+

IN–

010

IN–

IN+

010

IN–

IN+

010

IN–

IN+

010

IN–

IN+

011

IN–

IN+

011

IN–

IN+

011

IN–

IN+

011

IN–

IN+

100

IN+

IN–

100

IN+

IN–

100

IN+

IN–

100

IN+

IN–

101

IN+

IN–

101

IN+

IN–

101

IN+

IN–

101

IN+

IN–

110

IN+

IN–

110

IN+

IN–

110

IN+

IN–

110

IN+

IN–

111

IN+

IN–

111

IN+

IN–

111

IN+

IN–

111

IN+

IN–

*Default at power up

APPLICATIO S I FOR ATIO

maintain the parasitic capacitance of the connection be-

tween these series resistors and the corresponding pins

as low as possible; therefore, the resistors should be

located as close as practical to the pins. In addition, series

resistors will introduce a temperature dependent offset

error due to the input leakage current. A 10nA input

leakage current will develop a 1LBS offset error on an 8k

resistor if VREF = 5V. This error has a very strong tempera-

ture dependency.

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