CS44600 datasheet(77/78 Pages) CIRRUS

77 / 78 page

DS633PP1

CS44600

12.REVISION HISTORY

Release

Date

Changes

May 2004

1st Advance Release

September 2004

Updated lead-free device ordering information

October 2004

-Updated “Features” on page 1

-Updated “External Crystal operating frequency” on page 11

-Updated “Typical Full-Bridge Connection Diagram” on page 22

-Updated “Typical Half-Bridge Connection Diagram” on page 23

-Updated Section 4.2 "Feature Set Summary" on page 22

-Updated “FsOut Domain Clocking” on page 24

-Updated “Sample Rate Converter” on page 31

-Updated “PWM Engines” on page 32

-Updated Table 4, “Typical PWM Switch Rate Settings,” on page 33

-Updated Section 4.5.8 "Modulator" on page 33

-Updated Section 4.5.10 on page 34

-Updated Section 4.6.1 "SPI Mode" on page 35

-Updated Section 4.6.2 "I²C Mode" on page 36

-Updated Section 5. "Power Supply, Grounding, and PCB layout" on page 38

-Updated Section 5.1 "Reset and Power-Up" on page 41

-Updated Section 5.1.1 "PWM PopGuard® Transient Control" on page 41

-Updated Section 5.1.2 "Recommended Power-Up Sequence" on page 41

-Updated Section 5.1.3 "Recommended PSR Calibration Sequence" on page 42

-Updated Section 5.1.4 "Recommended Power-Down Sequence" on page 43

-Updated Section 6. "Register Quick Reference" on page 44

-Updated Section 7.5.2 "AM Frequency Hopping (AM_FREQ_HOP)" on page 51

-Updated Section 7.6 "Ramp Configuration (address 05h)" on page 52

-Updated Section 7.7.3 on page 53

-Corrected Table 7, “Master Fractional Volume Settings,” on page 56

-Corrected Table 9, “Channel Fractional Volume Settings,” on page 58

-Corrected Table 11, “Limiter Release Rate Settings,” on page 60

-Updated Table 7.18, “Chnl XX Load Compensation Filter - Coarse Adjust

(addresses 18h, 1Ah, 1Ch, 1Eh, 20h, 22h),” on page 60

-Updated Table 7.19, “Chnl XX Load Compensation Filter - Fine Adjust

(addresses 19h, 1Bh, 1Dh, 1Fh, 21h, 23h),” on page 61

-Updated Section 7.26 "GPIO Pin Level/Edge Trigger (address 2Eh)" on page 65

-Updated Section 7.29 "PWM Configuration Register (address 31h)" on page 66

PP1

May 2005

-Updated “Features” on page 1

-Updated “Ordering Information” on page 2

-Correcte “Power Supply Current” on page 9

-Corrected “High-Level Input Voltage” on page 9

-Corrected “Low-Level Input Voltage” on page 9

-Corrected “High-Level Output Voltage at Io = -2 mA” on page 9

-Corrected “Low-Level Output Voltage at Io = 2 mA” on page 9

-Corrected “Digital Filter Response (Note 12)” on page 11

-Updated “Typical Full-Bridge Connection Diagram” on page 22

-Updated “Typical Half-Bridge Connection Diagram” on page 23

-Corrected Figure 13 on page 23

-Updated Section 7.5.2 "AM Frequency Hopping (AM_FREQ_HOP)" on page 51

Table 19. Revision History

CS44600 Datasheet(PDF) 77 Page - Cirrus Logic

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