MPC852T datasheet(3/80 Pages) FREESCALE

3 / 80 page

MPC852T Hardware Specifications, Rev. 3.1

Freescale Semiconductor

Features

•

System integration unit (SIU)

— Bus monitor

— Software watchdog

— Periodic interrupt timer (PIT)

— Clock synthesizer

— Decrementer and time base

— Reset controller

— IEEE 1149.1 test access port (JTAG)

•

Interrupts

— Seven external interrupt request (IRQ) lines

— Seven port pins with interrupt capability

— Eighteen internal interrupt sources

— Programmable priority between SCCs

— Programmable highest-priority request

•

Communications processor module (CPM)

— RISC controller

— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and

RESTART TRANSMIT

)

— Supports continuous mode transmission and reception on all serial channels

— 8-Kbytes of dual-port RAM

— 8 serial DMA (SDMA) channels

— Three parallel I/O registers with open-drain capability

•

Two baud rate generators

— Independent (can be connected toany SCC3/4 or SMC1)

— Allows changes during operation

— Autobaud support option

•

Two SCCs (serial communication controllers)

— Ethernet/IEEE 802.3 optional on SCC3 & SCC4, supporting full 10-Mbps operation

— HDLC/SDLC

— HDLC bus (implements an HDLC-based local area network (LAN))

— Universal asynchronous receiver transmitter (UART)

— Totally transparent (bit streams)

— Totally transparent (frame-based with optional cyclic redundancy check (CRC))

•

One SMC (serial management channels)

— UART

•

One SPI (serial peripheral interface)

— Supports master and slave modes

— Supports multimaster operation on the same bus

•

PCMCIA interface

— Master (socket) interface, release 2.1 compliant

MPC852T Datasheet(PDF) 3 Page - Freescale Semiconductor, Inc

MPC852T Datasheet(HTML) 3 Page - Freescale Semiconductor, Inc

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