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CHRONTEL
CH7003B
201-0000-023 Rev 4.1, 8/2/99
7
Digital Video Interface (continued)
Non-multiplexed Mode
In the 15/16-bit mode shown in Figure 4, the pixel data bus represents a 15/16-bit non-multiplexed data stream,
which contains either RGB or YCrCb formatted data. When operating in RGB mode, each 15/16-bit Pn value will
contain a complete pixel encoded in either 5-6-5 or 5-5-5 format. When operating in YCrCb mode, each 16-bit Pn
word will contain an 8-bit Y (luminance) value on the upper 8 bits, and an 8-bit C (color difference) value on the
lower 8 bits. The color difference will be transmitted at half the data rate of the luminance data, with the sequence
being set as Cb followed by Cr. The Cb and Cr data will be co-sited with the Y value transmitted with the Cb value,
with the data sequence described in Table 3. The first active pixel is SAV pixels after the leading edge of horizontal
sync, where SAV is a bus-controlled register.
Figure 4: Non-multiplexed Data Transfers
Table 3. 15/16-bit Non-multiplexed Data Formats
IDF#
Format
0
RGB 5-6-5
3
RGB 5-5-5
1
YCrCb (16-bit)
Pixel#
P0
P1
P0
P1
P0
P1
P2
P3
Bus Data
D[15]
R0[4]
R1[4]
x
x
Y0[7]
Y1[7]
Y2[7]
Y3[7]
D[14]
R0[3]
R1[3]
R2[4]
R3[4]
Y0[6]
Y1[6]
Y2[6]
Y3[6]
D[13]
R0[2]
R1[2]
R2[3]
R3[3]
Y0[5]
Y1[5]
Y2[5]
Y3[5]
D[12]
R0[1]
R1[1]
R2[2]
R3[2]
Y0[4]
Y1[4]
Y2[4]
Y3[4]
D[11]
R0[0]
R1[0]
R2[1]
R3[1]
Y0[3]
Y1[3]
Y2[3]
Y3[3]
D[10]
G0[5]
G1[5]
R2[0]
R3[0]
Y0[2]
Y1[2]
Y2[2]
Y3[2]
D[9]
G0[4]
G1[4]
G2[4]
G3[4]
Y0[1]
Y1[1]
Y2[1]
Y3[1]
D[8]
G0[3]
G1[3]
G2[3]
G3[3]
Y0[0]
Y1[0]
Y2[0]
Y3[0]
D[7]
G0[2]
G1[2]
G2[2]
G3[2]
Cb0[7]
Cr0[7]
Cb2[7]
Cr2[7]
D[6]
G0[1]
G1[1]
G2[1]
G3[1]
Cb0[6]
Cr0[6]
Cb2[6]
Cr2[6]
D[5]
G0[0]
G1[0]
G2[0]
G3[0]
Cb0[5]
Cr0[5]
Cb2[5]
Cr2[5]
D[4]
B0[4]
B1[4]
B2[4]
B3[4]
Cb0[4]
Cr0[4]
Cb2[4]
Cr2[4]
D[3]
B0[3]
B1[3]
B2[3]
B3[3]
Cb0[3]
Cr0[3]
Cb2[3]
Cr2[3]
D[2]
B0[2]
B1[2]
B2[2]
B3[2]
Cb0[2]
Cr0[2]
Cb2[2]
Cr2[2]
D[1]
B0[1]
B1[1]
B2[1]
B3[1]
Cb0[1]
Cr0[1]
Cb2[1]
Cr2[1]
D[0]
B0[0]
B1[0]
B2[0]
B3[0]
Cb0[0]
Cr0[0]
Cb2[0]
Cr2[0]
t
HSW
Pixel
Data
POut/
XCLK
HSYNC
t
HD
P0a
P0b
P1a
P1b
P2a
P2b
t
PH
t
P
t
HP
t
SP
AVR
SAV
P0
P1
P2
P3
P4
P5
tP1
tPH 1
tHP1
t SP1
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