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BQ28Z610-R1

SLUSE07 – JANUARY 2020

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9.2.3 Application Curve

Figure 23. Elapsed Time(s)

10 Power Supply Recommendations

There are two inputs for this device, the PACK input and VC2. The PACK input can be an unregulated input from

a typical AC adapter. This input should always be greater than the maximum voltage associated with the number

of series cells configured. The input voltage for the VC2 pin will have a minimum of 2.2 V to a maximum of 26 V

with the recommended external RC filter.

11 Layout

11.1 Layout Guidelines

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The layout for the high-current path begins at the PACK+ pin of the battery pack. As charge current travels

through the pack, it finds its way through protection FETs, a chemical fuse, the Li-Ion cells and cell

connections, and the sense resistor, and then returns to the PACK– pin. In addition, some components are

placed across the PACK+ and PACK– pins to reduce effects from electrostatic discharge.

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The N-channel charge and discharge FETs must be selected for a given application. Most portable battery

applications are a good option for the CSD16412Q5A. These FETs are rated at 14-A, 25-V device with

Rds(on) of 11 mΩ when the gate drive voltage is 10 V. The gates of all protection FETs are pulled to the

source with a high-value resistor between the gate and source to ensure they are turned off if the gate drive

is open. The capacitors (both 0.1 µF values) placed across the FETs are to help protect the FETs during an

ESD event. The use of two devices ensures normal operation if one of them becomes shorted. For effective

ESD protection, the copper trace inductance of the capacitor leads must be designed to be as short and wide

as possible. Ensure that the voltage rating of both these capacitors is adequate to hold off the applied voltage

if one of the capacitors becomes shorted.

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The quality of the Kelvin connections at the sense resistor is critical. The sense resistor must have a