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ADP3189

Rev. 0 | Page 13 of 36

MASTER CLOCK FREQUENCY

The clock frequency of the ADP3189 is set with an external

resistor connected from the RT pin to ground. The frequency

follows the graph in Figure 6. To determine the frequency per

phase, the clock is divided by the number of phases in use. If

all phases are in use, divide by 5. If PWM5 is tied to VCC, then

divide the master clock by 4 for the frequency of the remaining

phases. If PWM4 and PWM5 are tied to VCC, then divide by 3.

If PWM3, PWM4, and PWM5 are tied to VCC, then divide

by 2.

OUTPUT VOLTAGE DIFFERENTIAL SENSING

The ADP3189 combines differential sensing with a high

accuracy VID DAC and reference and a low offset error ampli-

fier. This maintains a worst-case specification of ±7.7 mV

differential sensing error over its full operating output voltage

and temperature range. The output voltage is sensed between

the FB pin and FBRTN pin. FB should be connected through

a resistor to the regulation point, usually the remote sense pin

of the microprocessor. FBRTN should be connected directly

to the remote sense ground point. The internal VID DAC

and precision reference are referenced to FBRTN, which has

a minimal current of 125 μA to allow accurate remote sensing.

The internal error amplifier compares the output of the DAC

to the FB pin to regulate the output voltage.

OUTPUT CURRENT SENSING

The ADP3189 provides a dedicated current-sense amplifier

(CSA) to monitor the total output current for proper voltage

positioning vs. load current and for current-limit detection.

Sensing the load current at the output gives the total average

current being delivered to the load, which is an inherently more

accurate method than peak current detection or sampling the

current across a sense element such as the low-side MOSFET.

This amplifier can be configured several ways, depending on

the objectives of the system, as follows:

•

Output inductor DCR sensing without a thermistor for

lowest cost.

•

Output inductor DCR sensing with a thermistor for

improved accuracy with tracking of inductor temperature.

•

Sense resistors for highest accuracy measurements.

The positive input of the CSA is connected to the CSREF pin,

which is connected to the output voltage. The inputs to the

amplifier are summed together through resistors from the

sensing element, such as the switch node side of the output

inductors, to the inverting input, CSSUM. The feedback resistor

between CSCOMP and CSSUM sets the gain of the amplifier,

and a filter capacitor is placed in parallel with this resistor. The

gain of the amplifier is programmable by adjusting the feedback

resistor.

An additional resistor divider connected between CSREF and

CSCOMP, with the mid point connected to LLSET, can be used

to set the load line required by the microprocessor. The current

information is then given as CSREF – LLSET. This difference

signal is used internally to offset the VID DAC for voltage

positioning. The difference between CSREF and CSCOMP

is then used as a differential input for the current-limit

comparator. This allows for the load line to be set independ-

ently of the current-limit threshold. In the event that the

current limit threshold and load line are not independent,

the resistor divider between CSREF and CSCOMP can be

removed and the CSCOMP pin can be directly connected

to LLSET. To disable voltage positioning entirely (that is,

no load line) connect LLSET to CSREF.

To provide the best accuracy for sensing current, the CSA is

designed to have a low offset input voltage. Also, the sensing

gain is determined by external resistors, so that it can be made

extremely accurate.

ACTIVE IMPEDANCE CONTROL MODE

For controlling the dynamic output voltage droop as a function

of output current, a signal proportional to the total output current

at the LLSET pin can be scaled to be equal to the droop imped-

ance of the regulator times the output current. This droop voltage

is then used to set the input control voltage to the system. The

droop voltage is subtracted from the DAC reference input voltage

directly to tell the error amplifier where the output voltage should

be. This allows enhanced feed-forward response.

CURRENT CONTROL MODE AND THERMAL

BALANCE

The ADP3189 has individual inputs (SW1 to SW5) for each

phase, which are used for monitoring the current of each phase.

This information is combined with an internal ramp to create

a current balancing feedback system that has been optimized

for initial current balance accuracy and dynamic thermal

balancing during operation. This current balance information

is independent of the average output current information used

for positioning as described in the Output Current Sensing

section.

The magnitude of the internal ramp can be set to optimize the

transient response of the system. It also monitors the supply volt-

age for feed-forward control for changes in the supply. A resistor

connected from the power input voltage to the RAMPADJ pin

determines the slope of the internal PWM ramp. External

resistors can be placed in series with individual phases to

create an intentional current imbalance if desired, such as

when one phase has better cooling and can support higher

currents. Resistors RSW1 through RSW5 (see the Typical

Application Circuit in Figure 11) can be used for adjusting

thermal balance. It is best to have the ability to add these

resistors during the initial design, so ensure that placeholders

are provided in the layout.

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